From 2ed1c9f14ff4b7693c5ce308f9775d64737276b7 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 31 Mar 2022 17:00:38 +0000
Subject: [PATCH] Added SystemVerilog flag to fma.do so that fma16 compiles
 properly

---
 pipelined/src/fma/fma.do | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pipelined/src/fma/fma.do b/pipelined/src/fma/fma.do
index 6e6863d5f..4a23facf6 100644
--- a/pipelined/src/fma/fma.do
+++ b/pipelined/src/fma/fma.do
@@ -8,7 +8,7 @@ onbreak {resume}
 # create library
 vlib worklib
 
-vlog -lint -work worklib fma16.v testbench.v
+vlog -lint -sv -work worklib fma16.v testbench.v
 vopt +acc worklib.testbench_fma16 -work worklib -o testbenchopt
 vsim -lib worklib testbenchopt