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Fixed bug. After I$ invalidated. If the pipelined wasn't stalled the I$ still output the old instruction on the next cycle. Now the I$ ensure that invalidation leads to the next cycle not hitting.

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Rose Thompson 2024-01-17 12:19:10 -06:00
parent ed0f0d924b
commit 2d3dc55986
1 changed files with 4 additions and 1 deletions
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5
src/cache/cacheway.sv vendored
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@ -77,6 +77,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
logic ClearDirtyWay; logic ClearDirtyWay;
logic SelNonHit; logic SelNonHit;
logic SelData; logic SelData;
logic InvalidateCacheDelay;
if (!READ_ONLY_CACHE) begin:flushlogic if (!READ_ONLY_CACHE) begin:flushlogic
logic FlushWayEn; logic FlushWayEn;
@ -121,7 +122,9 @@ module cacheway import cvw::*; #(parameter cvw_t P,
assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux
assign HitDirtyWay = Dirty & ValidWay; assign HitDirtyWay = Dirty & ValidWay;
assign DirtyWay = SelDirty & HitDirtyWay; assign DirtyWay = SelDirty & HitDirtyWay;
assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]); assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]) & ~InvalidateCacheDelay;
flop #(1) InvalidateCacheReg(clk, InvalidateCache, InvalidateCacheDelay);
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Data Array // Data Array