From 2d3dc55986095dd0de45009139de1f40fd3c1215 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Wed, 17 Jan 2024 12:19:10 -0600
Subject: [PATCH] Fixed bug. After I$ invalidated.  If the pipelined wasn't
 stalled the I$ still output the old instruction on the next cycle.  Now the
 I$ ensure that invalidation leads to the next cycle not hitting.

---
 src/cache/cacheway.sv | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv
index 96762dbde..3445067a0 100644
--- a/src/cache/cacheway.sv
+++ b/src/cache/cacheway.sv
@@ -77,6 +77,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   logic                               ClearDirtyWay;
   logic                               SelNonHit;
   logic                               SelData;
+  logic                               InvalidateCacheDelay;
   
   if (!READ_ONLY_CACHE) begin:flushlogic
     logic                               FlushWayEn;
@@ -121,7 +122,9 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux
   assign HitDirtyWay = Dirty & ValidWay;
   assign DirtyWay = SelDirty & HitDirtyWay;
-  assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]);
+  assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]) & ~InvalidateCacheDelay;
+
+  flop #(1) InvalidateCacheReg(clk, InvalidateCache, InvalidateCacheDelay);
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Data Array