mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
change flop in ahb controller to use normal flop module
This commit is contained in:
parent
0baa004bb4
commit
2d1f63b590
@ -84,9 +84,7 @@ module ahblite (
|
|||||||
typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADMEMPENDING} statetype;
|
typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADMEMPENDING} statetype;
|
||||||
statetype BusState, NextBusState;
|
statetype BusState, NextBusState;
|
||||||
|
|
||||||
always_ff @(posedge HCLK, negedge HRESETn)
|
flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);
|
||||||
if (~HRESETn) BusState <= #1 IDLE;
|
|
||||||
else BusState <= #1 NextBusState;
|
|
||||||
|
|
||||||
always_comb
|
always_comb
|
||||||
case (BusState)
|
case (BusState)
|
||||||
|
@ -82,11 +82,11 @@ module flopenr #(parameter WIDTH = 8) (
|
|||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
// flop with enable, asynchronous load
|
// flop with enable, asynchronous load
|
||||||
module flopenl #(parameter WIDTH = 8) (
|
module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
|
||||||
input logic clk, load, en,
|
input logic clk, load, en,
|
||||||
input logic [WIDTH-1:0] d,
|
input TYPE d,
|
||||||
input logic [WIDTH-1:0] val,
|
input TYPE val,
|
||||||
output logic [WIDTH-1:0] q);
|
output TYPE q);
|
||||||
|
|
||||||
always_ff @(posedge clk, posedge load)
|
always_ff @(posedge clk, posedge load)
|
||||||
if (load) q <= #1 val;
|
if (load) q <= #1 val;
|
||||||
|
Loading…
Reference in New Issue
Block a user