diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index ad604be54..07918cdb2 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -84,9 +84,7 @@ module ahblite ( typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADMEMPENDING} statetype; statetype BusState, NextBusState; - always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) BusState <= #1 IDLE; - else BusState <= #1 NextBusState; + flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState); always_comb case (BusState) diff --git a/wally-pipelined/src/generic/flop.sv b/wally-pipelined/src/generic/flop.sv index 7e954a8f8..a5636c6f4 100644 --- a/wally-pipelined/src/generic/flop.sv +++ b/wally-pipelined/src/generic/flop.sv @@ -82,11 +82,11 @@ module flopenr #(parameter WIDTH = 8) ( endmodule // flop with enable, asynchronous load -module flopenl #(parameter WIDTH = 8) ( - input logic clk, load, en, - input logic [WIDTH-1:0] d, - input logic [WIDTH-1:0] val, - output logic [WIDTH-1:0] q); +module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) ( + input logic clk, load, en, + input TYPE d, + input TYPE val, + output TYPE q); always_ff @(posedge clk, posedge load) if (load) q <= #1 val;