fixed InstrValid signals and implemented less costly MEPC loading

This commit is contained in:
bbracker 2021-06-02 10:03:19 -04:00
parent 39ae743543
commit 2c77a13c08
8 changed files with 39 additions and 39 deletions

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@ -24,10 +24,12 @@ add wave -divider
add wave -hex /testbench/dut/hart/ifu/PCF add wave -hex /testbench/dut/hart/ifu/PCF
add wave -hex /testbench/dut/hart/ifu/PCD add wave -hex /testbench/dut/hart/ifu/PCD
add wave -hex /testbench/dut/hart/ifu/InstrD add wave -hex /testbench/dut/hart/ifu/InstrD
add wave -hex /testbench/dut/hart/ieu/c/InstrValidD
add wave /testbench/InstrDName add wave /testbench/InstrDName
add wave -divider add wave -divider
add wave -hex /testbench/dut/hart/ifu/PCE add wave -hex /testbench/dut/hart/ifu/PCE
add wave -hex /testbench/dut/hart/ifu/InstrE add wave -hex /testbench/dut/hart/ifu/InstrE
add wave -hex /testbench/dut/hart/ieu/c/InstrValidE
add wave /testbench/InstrEName add wave /testbench/InstrEName
add wave -hex /testbench/dut/hart/ieu/dp/SrcAE add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
add wave -hex /testbench/dut/hart/ieu/dp/SrcBE add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
@ -36,6 +38,7 @@ add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
add wave -divider add wave -divider
add wave -hex /testbench/dut/hart/ifu/PCM add wave -hex /testbench/dut/hart/ifu/PCM
add wave -hex /testbench/dut/hart/ifu/InstrM add wave -hex /testbench/dut/hart/ifu/InstrM
add wave -hex /testbench/dut/hart/ieu/c/InstrValidM
add wave /testbench/InstrMName add wave /testbench/InstrMName
add wave /testbench/dut/uncore/dtim/memwrite add wave /testbench/dut/uncore/dtim/memwrite
add wave -hex /testbench/dut/uncore/HADDR add wave -hex /testbench/dut/uncore/HADDR
@ -43,12 +46,12 @@ add wave -hex /testbench/dut/uncore/HWDATA
add wave -divider add wave -divider
add wave -hex /testbench/PCW add wave -hex /testbench/PCW
add wave -hex /testbench/InstrW add wave -hex /testbench/InstrW
add wave -hex /testbench/dut/hart/ieu/c/InstrValidW
add wave /testbench/InstrWName add wave /testbench/InstrWName
add wave /testbench/dut/hart/ieu/dp/RegWriteW add wave /testbench/dut/hart/ieu/dp/RegWriteW
add wave -hex /testbench/dut/hart/ieu/dp/ResultW add wave -hex /testbench/dut/hart/ieu/dp/ResultW
add wave -hex /testbench/dut/hart/ieu/dp/RdW add wave -hex /testbench/dut/hart/ieu/dp/RdW
add wave -divider add wave -divider
add wave -hex /testbench/dut/hart/priv/csr/ProposedEPCM
add wave -hex /testbench/dut/hart/priv/csr/TrapM add wave -hex /testbench/dut/hart/priv/csr/TrapM
add wave -hex /testbench/dut/hart/priv/csr/UnalignedNextEPCM add wave -hex /testbench/dut/hart/priv/csr/UnalignedNextEPCM
add wave -hex /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMEPCM add wave -hex /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMEPCM

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@ -48,6 +48,7 @@ module dmem (
input logic [`XLEN-1:0] ReadDataW, input logic [`XLEN-1:0] ReadDataW,
output logic SquashSCW, output logic SquashSCW,
// faults // faults
input logic NonBusTrapM,
input logic DataAccessFaultM, input logic DataAccessFaultM,
output logic DTLBLoadPageFaultM, DTLBStorePageFaultM, output logic DTLBLoadPageFaultM, DTLBStorePageFaultM,
output logic LoadMisalignedFaultM, LoadAccessFaultM, output logic LoadMisalignedFaultM, LoadAccessFaultM,
@ -95,8 +96,11 @@ module dmem (
// Squash unaligned data accesses and failed store conditionals // Squash unaligned data accesses and failed store conditionals
// *** this is also the place to squash if the cache is hit // *** this is also the place to squash if the cache is hit
assign MemReadM = MemRWM[1] & ~DataMisalignedM & CurrState != STATE_STALLED; // Changed DataMisalignedM to a larger combination of trap sources
assign MemWriteM = MemRWM[0] & ~DataMisalignedM && ~SquashSCM & CurrState != STATE_STALLED; // NonBusTrapM is anything that the bus doesn't contribute to producing
// By contrast, using TrapM results in circular logic errors
assign MemReadM = MemRWM[1] & ~NonBusTrapM & CurrState != STATE_STALLED;
assign MemWriteM = MemRWM[0] & ~NonBusTrapM && ~SquashSCM & CurrState != STATE_STALLED;
assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicM : 2'b00 ; assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicM : 2'b00 ;
assign MemAccessM = |MemRWM; assign MemAccessM = |MemRWM;

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@ -29,6 +29,7 @@
module controller( module controller(
input logic clk, reset, input logic clk, reset,
// Decode stage control signals // Decode stage control signals
input logic StallD, FlushD,
input logic [31:0] InstrD, input logic [31:0] InstrD,
output logic [2:0] ImmSrcD, output logic [2:0] ImmSrcD,
input logic IllegalIEUInstrFaultD, input logic IllegalIEUInstrFaultD,
@ -52,6 +53,7 @@ module controller(
output logic [1:0] AtomicM, output logic [1:0] AtomicM,
output logic [2:0] Funct3M, output logic [2:0] Funct3M,
output logic RegWriteM, // for Hazard Unit output logic RegWriteM, // for Hazard Unit
output logic InstrValidM,
// Writeback stage control signals // Writeback stage control signals
input logic StallW, FlushW, input logic StallW, FlushW,
output logic RegWriteW, // for datapath and Hazard Unit output logic RegWriteW, // for datapath and Hazard Unit
@ -82,7 +84,7 @@ module controller(
logic CSRReadD; logic CSRReadD;
logic [1:0] AtomicD, AtomicE; logic [1:0] AtomicD, AtomicE;
logic CSRWriteD, CSRWriteE; logic CSRWriteD, CSRWriteE;
logic InstrValidE, InstrValidM; logic InstrValidD, InstrValidE;
logic PrivilegedD, PrivilegedE; logic PrivilegedD, PrivilegedE;
logic [`CTRLW-1:0] ControlsD; logic [`CTRLW-1:0] ControlsD;
logic aluc3D; logic aluc3D;
@ -176,9 +178,12 @@ module controller(
default: ALUControlD = {W64D, aluc3D, Funct3D}; // R-type instructions default: ALUControlD = {W64D, aluc3D, Funct3D}; // R-type instructions
endcase endcase
// Decocde stage pipeline control register
flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
// Execute stage pipeline control register and logic // Execute stage pipeline control register and logic
flopenrc #(27) controlregE(clk, reset, FlushE, ~StallE, flopenrc #(27) controlregE(clk, reset, FlushE, ~StallE,
{RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, TargetSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MulDivD, AtomicD, 1'b1}, {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, TargetSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MulDivD, AtomicD, InstrValidD},
{RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, TargetSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InstrValidE}); {RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, TargetSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InstrValidE});
// Branch Logic // Branch Logic

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@ -56,10 +56,10 @@ module ieu (
input logic FWriteIntW, input logic FWriteIntW,
input logic [`XLEN-1:0] FPUResultW, input logic [`XLEN-1:0] FPUResultW,
// input logic [`XLEN-1:0] PCLinkW, // input logic [`XLEN-1:0] PCLinkW,
output logic InstrValidW, output logic InstrValidM, InstrValidW,
// hazards // hazards
input logic StallE, StallM, StallW, input logic StallD, StallE, StallM, StallW,
input logic FlushE, FlushM, FlushW, input logic FlushD, FlushE, FlushM, FlushW,
output logic FPUStallD, LoadStallD, MulDivStallD, CSRRdStallD, output logic FPUStallD, LoadStallD, MulDivStallD, CSRRdStallD,
output logic PCSrcE, output logic PCSrcE,
input logic DivDoneE, input logic DivDoneE,

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@ -77,8 +77,7 @@ module csr #(parameter
logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM; logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM;
logic CSRMWriteM, CSRSWriteM, CSRUWriteM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM;
logic MStageFailed; logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM;
logic [`XLEN-1:0] ProposedEPCM, UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM;
logic [11:0] CSRAdrM; logic [11:0] CSRAdrM;
logic [11:0] SIP_REGW, SIE_REGW; logic [11:0] SIP_REGW, SIE_REGW;
@ -86,23 +85,6 @@ module csr #(parameter
logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, IllegalCSRNAccessM, InsufficientCSRPrivilegeM; logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, IllegalCSRNAccessM, InsufficientCSRPrivilegeM;
logic IllegalCSRMWriteReadonlyM; logic IllegalCSRMWriteReadonlyM;
assign MStageFailed = BreakpointFaultM || EcallFaultM || InstrMisalignedFaultM || InstrAccessFaultM || IllegalInstrFaultM || LoadMisalignedFaultM || StoreMisalignedFaultM || LoadAccessFaultM || StoreAccessFaultM;
always_comb begin
if (MStageFailed)
casez({InstrD==NOP,InstrE==NOP,InstrM==NOP})
3'b??0: ProposedEPCM = PCM;
3'b?01: ProposedEPCM = PCE;
3'b011: ProposedEPCM = PCD;
3'b111: ProposedEPCM = PCF;
endcase
else
casez({InstrD==NOP,InstrE==NOP})
2'b?0: ProposedEPCM = PCE;
2'b01: ProposedEPCM = PCD;
2'b11: ProposedEPCM = PCF;
endcase
end
generate generate
if (`ZCSR_SUPPORTED) begin if (`ZCSR_SUPPORTED) begin
// modify CSRs // modify CSRs
@ -123,7 +105,7 @@ module csr #(parameter
// write CSRs // write CSRs
assign CSRAdrM = InstrM[31:20]; assign CSRAdrM = InstrM[31:20];
assign UnalignedNextEPCM = TrapM ? ProposedEPCM : CSRWriteValM; assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM;
assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
assign NextCauseM = TrapM ? CauseM : CSRWriteValM; assign NextCauseM = TrapM ? CauseM : CSRWriteValM;
assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;

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@ -35,9 +35,9 @@ module privileged (
input logic [31:0] InstrD, InstrE, InstrM, InstrW, input logic [31:0] InstrD, InstrE, InstrM, InstrW,
output logic [`XLEN-1:0] CSRReadValW, output logic [`XLEN-1:0] CSRReadValW,
output logic [`XLEN-1:0] PrivilegedNextPCM, output logic [`XLEN-1:0] PrivilegedNextPCM,
output logic RetM, TrapM, output logic RetM, TrapM, NonBusTrapM,
output logic ITLBFlushF, DTLBFlushM, output logic ITLBFlushF, DTLBFlushM,
input logic InstrValidW, FloatRegWriteW, LoadStallD, input logic InstrValidM,InstrValidW, FloatRegWriteW, LoadStallD,
input logic BPPredDirWrongM, input logic BPPredDirWrongM,
input logic BTBPredPCWrongM, input logic BTBPredPCWrongM,
input logic RASPredPCWrongM, input logic RASPredPCWrongM,

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@ -41,7 +41,8 @@ module trap (
input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
input logic [31:0] InstrM, input logic [31:0] InstrM,
input logic StallW, input logic StallW,
output logic TrapM, MTrapM, STrapM, UTrapM, RetM, input logic InstrValidM,
output logic NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM,
output logic InterruptM, output logic InterruptM,
output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
@ -51,18 +52,23 @@ module trap (
logic [11:0] MIntGlobalEnM, SIntGlobalEnM, PendingIntsM; logic [11:0] MIntGlobalEnM, SIntGlobalEnM, PendingIntsM;
//logic InterruptM; //logic InterruptM;
logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
logic BusTrapM;
// Determine pending enabled interrupts // Determine pending enabled interrupts
assign MIntGlobalEnM = {12{(PrivilegeModeW != `M_MODE) || STATUS_MIE}}; // if M ints enabled or lower priv 3.1.9 assign MIntGlobalEnM = {12{(PrivilegeModeW != `M_MODE) || STATUS_MIE}}; // if M ints enabled or lower priv 3.1.9
assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9 assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9
assign PendingIntsM = (MIP_REGW & MIE_REGW) & ((MIntGlobalEnM & 12'h888) | (SIntGlobalEnM & 12'h222)); assign PendingIntsM = (MIP_REGW & MIE_REGW) & ((MIntGlobalEnM & 12'h888) | (SIntGlobalEnM & 12'h222));
assign InterruptM = |PendingIntsM; // interrupt if any sources are pending assign InterruptM = (|PendingIntsM) && InstrValidM; // interrupt if any sources are pending // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
// Trigger Traps and RET // Trigger Traps and RET
assign TrapM = InstrMisalignedFaultM | InstrAccessFaultM | IllegalInstrFaultM | // Created groups of trap signals so that bus could take in all traps it doesn't already produce (i.e. using just TrapM to squash access created circular paths)
BreakpointFaultM | LoadMisalignedFaultM | StoreMisalignedFaultM | assign BusTrapM = LoadAccessFaultM | StoreAccessFaultM;
LoadAccessFaultM | StoreAccessFaultM | EcallFaultM | InstrPageFaultM | assign NonBusTrapM = InstrMisalignedFaultM | InstrAccessFaultM | IllegalInstrFaultM |
LoadPageFaultM | StorePageFaultM | InterruptM; LoadMisalignedFaultM | StoreMisalignedFaultM |
InstrPageFaultM | LoadPageFaultM | StorePageFaultM |
BreakpointFaultM | EcallFaultM |
InterruptM;
assign TrapM = BusTrapM | NonBusTrapM;
assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
assign UTrapM = TrapM & (NextPrivilegeModeM == `U_MODE) & `N_SUPPORTED; assign UTrapM = TrapM & (NextPrivilegeModeM == `U_MODE) & `N_SUPPORTED;

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@ -58,7 +58,7 @@ module wallypipelinedhart (
// logic [1:0] ForwardAE, ForwardBE; // logic [1:0] ForwardAE, ForwardBE;
logic StallF, StallD, StallE, StallM, StallW; logic StallF, StallD, StallE, StallM, StallW;
logic FlushF, FlushD, FlushE, FlushM, FlushW; logic FlushF, FlushD, FlushE, FlushM, FlushW;
logic RetM, TrapM; logic RetM, TrapM, NonBusTrapM;
// new signals that must connect through DP // new signals that must connect through DP
logic MulDivE, W64E; logic MulDivE, W64E;
@ -74,7 +74,7 @@ module wallypipelinedhart (
logic [`XLEN-1:0] CSRReadValW, MulDivResultW; logic [`XLEN-1:0] CSRReadValW, MulDivResultW;
logic [`XLEN-1:0] PrivilegedNextPCM; logic [`XLEN-1:0] PrivilegedNextPCM;
logic [1:0] MemRWM; logic [1:0] MemRWM;
logic InstrValidW; logic InstrValidM, InstrValidW;
logic InstrMisalignedFaultM; logic InstrMisalignedFaultM;
logic DataMisalignedM; logic DataMisalignedM;
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;