From 2c77a13c0805666b5bd7069963a7f4379ebc3202 Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 2 Jun 2021 10:03:19 -0400 Subject: [PATCH] fixed InstrValid signals and implemented less costly MEPC loading --- .../regression/wave-dos/peripheral-waves.do | 5 ++++- wally-pipelined/src/dmem/dmem.sv | 8 +++++-- wally-pipelined/src/ieu/controller.sv | 11 +++++++--- wally-pipelined/src/ieu/ieu.sv | 6 ++--- wally-pipelined/src/privileged/csr.sv | 22 ++----------------- wally-pipelined/src/privileged/privileged.sv | 4 ++-- wally-pipelined/src/privileged/trap.sv | 18 ++++++++++----- .../src/wally/wallypipelinedhart.sv | 4 ++-- 8 files changed, 39 insertions(+), 39 deletions(-) diff --git a/wally-pipelined/regression/wave-dos/peripheral-waves.do b/wally-pipelined/regression/wave-dos/peripheral-waves.do index 3c4945c7d..a27caf293 100644 --- a/wally-pipelined/regression/wave-dos/peripheral-waves.do +++ b/wally-pipelined/regression/wave-dos/peripheral-waves.do @@ -24,10 +24,12 @@ add wave -divider add wave -hex /testbench/dut/hart/ifu/PCF add wave -hex /testbench/dut/hart/ifu/PCD add wave -hex /testbench/dut/hart/ifu/InstrD +add wave -hex /testbench/dut/hart/ieu/c/InstrValidD add wave /testbench/InstrDName add wave -divider add wave -hex /testbench/dut/hart/ifu/PCE add wave -hex /testbench/dut/hart/ifu/InstrE +add wave -hex /testbench/dut/hart/ieu/c/InstrValidE add wave /testbench/InstrEName add wave -hex /testbench/dut/hart/ieu/dp/SrcAE add wave -hex /testbench/dut/hart/ieu/dp/SrcBE @@ -36,6 +38,7 @@ add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE add wave -divider add wave -hex /testbench/dut/hart/ifu/PCM add wave -hex /testbench/dut/hart/ifu/InstrM +add wave -hex /testbench/dut/hart/ieu/c/InstrValidM add wave /testbench/InstrMName add wave /testbench/dut/uncore/dtim/memwrite add wave -hex /testbench/dut/uncore/HADDR @@ -43,12 +46,12 @@ add wave -hex /testbench/dut/uncore/HWDATA add wave -divider add wave -hex /testbench/PCW add wave -hex /testbench/InstrW +add wave -hex /testbench/dut/hart/ieu/c/InstrValidW add wave /testbench/InstrWName add wave /testbench/dut/hart/ieu/dp/RegWriteW add wave -hex /testbench/dut/hart/ieu/dp/ResultW add wave -hex /testbench/dut/hart/ieu/dp/RdW add wave -divider -add wave -hex /testbench/dut/hart/priv/csr/ProposedEPCM add wave -hex /testbench/dut/hart/priv/csr/TrapM add wave -hex /testbench/dut/hart/priv/csr/UnalignedNextEPCM add wave -hex /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMEPCM diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index 506583a04..67569f2e2 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -48,6 +48,7 @@ module dmem ( input logic [`XLEN-1:0] ReadDataW, output logic SquashSCW, // faults + input logic NonBusTrapM, input logic DataAccessFaultM, output logic DTLBLoadPageFaultM, DTLBStorePageFaultM, output logic LoadMisalignedFaultM, LoadAccessFaultM, @@ -95,8 +96,11 @@ module dmem ( // Squash unaligned data accesses and failed store conditionals // *** this is also the place to squash if the cache is hit - assign MemReadM = MemRWM[1] & ~DataMisalignedM & CurrState != STATE_STALLED; - assign MemWriteM = MemRWM[0] & ~DataMisalignedM && ~SquashSCM & CurrState != STATE_STALLED; + // Changed DataMisalignedM to a larger combination of trap sources + // NonBusTrapM is anything that the bus doesn't contribute to producing + // By contrast, using TrapM results in circular logic errors + assign MemReadM = MemRWM[1] & ~NonBusTrapM & CurrState != STATE_STALLED; + assign MemWriteM = MemRWM[0] & ~NonBusTrapM && ~SquashSCM & CurrState != STATE_STALLED; assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicM : 2'b00 ; assign MemAccessM = |MemRWM; diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index e73fc6848..9a877f4be 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -29,6 +29,7 @@ module controller( input logic clk, reset, // Decode stage control signals + input logic StallD, FlushD, input logic [31:0] InstrD, output logic [2:0] ImmSrcD, input logic IllegalIEUInstrFaultD, @@ -51,7 +52,8 @@ module controller( output logic CSRReadM, CSRWriteM, PrivilegedM, output logic [1:0] AtomicM, output logic [2:0] Funct3M, - output logic RegWriteM, // for Hazard Unit + output logic RegWriteM, // for Hazard Unit + output logic InstrValidM, // Writeback stage control signals input logic StallW, FlushW, output logic RegWriteW, // for datapath and Hazard Unit @@ -82,7 +84,7 @@ module controller( logic CSRReadD; logic [1:0] AtomicD, AtomicE; logic CSRWriteD, CSRWriteE; - logic InstrValidE, InstrValidM; + logic InstrValidD, InstrValidE; logic PrivilegedD, PrivilegedE; logic [`CTRLW-1:0] ControlsD; logic aluc3D; @@ -176,9 +178,12 @@ module controller( default: ALUControlD = {W64D, aluc3D, Funct3D}; // R-type instructions endcase + // Decocde stage pipeline control register + flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); + // Execute stage pipeline control register and logic flopenrc #(27) controlregE(clk, reset, FlushE, ~StallE, - {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, TargetSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MulDivD, AtomicD, 1'b1}, + {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, TargetSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MulDivD, AtomicD, InstrValidD}, {RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, TargetSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InstrValidE}); // Branch Logic diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index a4ab9b063..0bd9d598f 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -56,10 +56,10 @@ module ieu ( input logic FWriteIntW, input logic [`XLEN-1:0] FPUResultW, // input logic [`XLEN-1:0] PCLinkW, - output logic InstrValidW, + output logic InstrValidM, InstrValidW, // hazards - input logic StallE, StallM, StallW, - input logic FlushE, FlushM, FlushW, + input logic StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, output logic FPUStallD, LoadStallD, MulDivStallD, CSRRdStallD, output logic PCSrcE, input logic DivDoneE, diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index 89d71fb5b..fd7f204eb 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -77,31 +77,13 @@ module csr #(parameter logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM; - logic MStageFailed; - logic [`XLEN-1:0] ProposedEPCM, UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM; + logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM; logic [11:0] CSRAdrM; logic [11:0] SIP_REGW, SIE_REGW; //logic [11:0] UIP_REGW, UIE_REGW = 0; // N user-mode exceptions not supported logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, IllegalCSRNAccessM, InsufficientCSRPrivilegeM; logic IllegalCSRMWriteReadonlyM; - - assign MStageFailed = BreakpointFaultM || EcallFaultM || InstrMisalignedFaultM || InstrAccessFaultM || IllegalInstrFaultM || LoadMisalignedFaultM || StoreMisalignedFaultM || LoadAccessFaultM || StoreAccessFaultM; - always_comb begin - if (MStageFailed) - casez({InstrD==NOP,InstrE==NOP,InstrM==NOP}) - 3'b??0: ProposedEPCM = PCM; - 3'b?01: ProposedEPCM = PCE; - 3'b011: ProposedEPCM = PCD; - 3'b111: ProposedEPCM = PCF; - endcase - else - casez({InstrD==NOP,InstrE==NOP}) - 2'b?0: ProposedEPCM = PCE; - 2'b01: ProposedEPCM = PCD; - 2'b11: ProposedEPCM = PCF; - endcase - end generate if (`ZCSR_SUPPORTED) begin @@ -123,7 +105,7 @@ module csr #(parameter // write CSRs assign CSRAdrM = InstrM[31:20]; - assign UnalignedNextEPCM = TrapM ? ProposedEPCM : CSRWriteValM; + assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM; assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment assign NextCauseM = TrapM ? CauseM : CSRWriteValM; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 41d685c41..a29fb56e6 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -35,9 +35,9 @@ module privileged ( input logic [31:0] InstrD, InstrE, InstrM, InstrW, output logic [`XLEN-1:0] CSRReadValW, output logic [`XLEN-1:0] PrivilegedNextPCM, - output logic RetM, TrapM, + output logic RetM, TrapM, NonBusTrapM, output logic ITLBFlushF, DTLBFlushM, - input logic InstrValidW, FloatRegWriteW, LoadStallD, + input logic InstrValidM,InstrValidW, FloatRegWriteW, LoadStallD, input logic BPPredDirWrongM, input logic BTBPredPCWrongM, input logic RASPredPCWrongM, diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv index 36cde4dad..ee696d829 100644 --- a/wally-pipelined/src/privileged/trap.sv +++ b/wally-pipelined/src/privileged/trap.sv @@ -41,7 +41,8 @@ module trap ( input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [31:0] InstrM, input logic StallW, - output logic TrapM, MTrapM, STrapM, UTrapM, RetM, + input logic InstrValidM, + output logic NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM, output logic InterruptM, output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, @@ -51,18 +52,23 @@ module trap ( logic [11:0] MIntGlobalEnM, SIntGlobalEnM, PendingIntsM; //logic InterruptM; logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; + logic BusTrapM; // Determine pending enabled interrupts assign MIntGlobalEnM = {12{(PrivilegeModeW != `M_MODE) || STATUS_MIE}}; // if M ints enabled or lower priv 3.1.9 assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9 assign PendingIntsM = (MIP_REGW & MIE_REGW) & ((MIntGlobalEnM & 12'h888) | (SIntGlobalEnM & 12'h222)); - assign InterruptM = |PendingIntsM; // interrupt if any sources are pending + assign InterruptM = (|PendingIntsM) && InstrValidM; // interrupt if any sources are pending // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage) // Trigger Traps and RET - assign TrapM = InstrMisalignedFaultM | InstrAccessFaultM | IllegalInstrFaultM | - BreakpointFaultM | LoadMisalignedFaultM | StoreMisalignedFaultM | - LoadAccessFaultM | StoreAccessFaultM | EcallFaultM | InstrPageFaultM | - LoadPageFaultM | StorePageFaultM | InterruptM; + // Created groups of trap signals so that bus could take in all traps it doesn't already produce (i.e. using just TrapM to squash access created circular paths) + assign BusTrapM = LoadAccessFaultM | StoreAccessFaultM; + assign NonBusTrapM = InstrMisalignedFaultM | InstrAccessFaultM | IllegalInstrFaultM | + LoadMisalignedFaultM | StoreMisalignedFaultM | + InstrPageFaultM | LoadPageFaultM | StorePageFaultM | + BreakpointFaultM | EcallFaultM | + InterruptM; + assign TrapM = BusTrapM | NonBusTrapM; assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; assign UTrapM = TrapM & (NextPrivilegeModeM == `U_MODE) & `N_SUPPORTED; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 00ae84933..aa252e377 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -58,7 +58,7 @@ module wallypipelinedhart ( // logic [1:0] ForwardAE, ForwardBE; logic StallF, StallD, StallE, StallM, StallW; logic FlushF, FlushD, FlushE, FlushM, FlushW; - logic RetM, TrapM; + logic RetM, TrapM, NonBusTrapM; // new signals that must connect through DP logic MulDivE, W64E; @@ -74,7 +74,7 @@ module wallypipelinedhart ( logic [`XLEN-1:0] CSRReadValW, MulDivResultW; logic [`XLEN-1:0] PrivilegedNextPCM; logic [1:0] MemRWM; - logic InstrValidW; + logic InstrValidM, InstrValidW; logic InstrMisalignedFaultM; logic DataMisalignedM; logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;