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Timinig optimization for radix 4 division, added missing derived config

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David Harris 2024-03-06 15:05:04 -08:00
parent 0f93d00977
commit 2c6588d4ae
2 changed files with 29 additions and 2 deletions
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4
config/derivlist.txt
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@ -546,6 +546,10 @@ deriv fd_rv64gc rv64gc
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
deriv fdh_rv64gc rv64gc
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdq_rv64gc rv64gc deriv fdq_rv64gc rv64gc
MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0

27
src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv
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@ -48,10 +48,10 @@ module fdivsqrtuslc4cmp (
logic [6:0] mk2, mk1, mk0, mkm1; logic [6:0] mk2, mk1, mk0, mkm1;
logic [6:0] mkj2, mkj1, mkj0, mkjm1; logic [6:0] mkj2, mkj1, mkj0, mkjm1;
logic [6:0] mks2[7:0], mks1[7:0]; logic [6:0] mks2[7:0], mks1[7:0], mks0[7:0], mksm1[7:0];
logic sqrtspecial; logic sqrtspecial;
// Prepopulate table of mks0 // Prepopulate table of mks for comparison
assign mks2[0] = 12; assign mks2[0] = 12;
assign mks2[1] = 14; assign mks2[1] = 14;
assign mks2[2] = 16; assign mks2[2] = 16;
@ -69,6 +69,24 @@ module fdivsqrtuslc4cmp (
assign mks1[6] = 8; assign mks1[6] = 8;
assign mks1[7] = 8; assign mks1[7] = 8;
assign mks0[0] = -4;
assign mks0[1] = -4;
assign mks0[2] = -6;
assign mks0[3] = -6;
assign mks0[4] = -6;
assign mks0[5] = -8;
assign mks0[6] = -8;
assign mks0[7] = -8;
assign mksm1[0] = -13;
assign mksm1[1] = -14;
assign mksm1[2] = -16;
assign mksm1[3] = -17;
assign mksm1[4] = -18;
assign mksm1[5] = -20;
assign mksm1[6] = -22;
assign mksm1[7] = -23;
// handles special case when j = 0 or j = 1 for sqrt // handles special case when j = 0 or j = 1 for sqrt
assign mkj2 = 20; // when j = 1 use mk2[101] when j = 0 use anything bigger than 7. assign mkj2 = 20; // when j = 1 use mk2[101] when j = 0 use anything bigger than 7.
assign mkj1 = j0 ? 0 : 8; // when j = 1 use mk1[101] = 8 and when j = 0 use 0 so we choose u_0 = 1 assign mkj1 = j0 ? 0 : 8; // when j = 1 use mk1[101] = 8 and when j = 0 use 0 so we choose u_0 = 1
@ -85,8 +103,13 @@ module fdivsqrtuslc4cmp (
assign mk2 = sqrtspecial ? mkj2 : mks2[A]; assign mk2 = sqrtspecial ? mkj2 : mks2[A];
assign mk1 = sqrtspecial ? mkj1 : mks1[A]; assign mk1 = sqrtspecial ? mkj1 : mks1[A];
assign mk0 = sqrtspecial ? -mkj1 : mks0[A];
assign mkm1 = sqrtspecial ? -mkj2 : mksm1[A];
/* Nannarelli12 design to exploit symmetry is slower because of negation and mux for special case of A = 000
assign mk0 = -mk1; assign mk0 = -mk1;
assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table *** can we hide from critical path assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table *** can we hide from critical path
*/
// Compare residual W to selection constants to choose digit // Compare residual W to selection constants to choose digit
always_comb always_comb