From 2c6588d4ae0c18522b7e82f10a62865285f23d3d Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Wed, 6 Mar 2024 15:05:04 -0800
Subject: [PATCH] Timinig optimization for radix 4 division, added missing
 derived config

---
 config/derivlist.txt                 |  4 ++++
 src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv | 27 +++++++++++++++++++++++++--
 2 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/config/derivlist.txt b/config/derivlist.txt
index 279fbd3c5..6851278b3 100644
--- a/config/derivlist.txt
+++ b/config/derivlist.txt
@@ -546,6 +546,10 @@ deriv fd_rv64gc rv64gc
 MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
+deriv fdh_rv64gc rv64gc
+MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+ZFH_SUPPORTED   1
+
 deriv fdq_rv64gc rv64gc
 MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
diff --git a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv
index fef26668c..fd1092497 100644
--- a/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv
@@ -48,10 +48,10 @@ module fdivsqrtuslc4cmp (
 
   logic [6:0] mk2, mk1, mk0, mkm1;
   logic [6:0] mkj2, mkj1, mkj0, mkjm1;
-  logic [6:0] mks2[7:0], mks1[7:0]; 
+  logic [6:0] mks2[7:0], mks1[7:0], mks0[7:0], mksm1[7:0];
   logic sqrtspecial;
 
-  // Prepopulate table of mks0
+  // Prepopulate table of mks for comparison
   assign mks2[0] = 12;
   assign mks2[1] = 14;
   assign mks2[2] = 16;
@@ -68,6 +68,24 @@ module fdivsqrtuslc4cmp (
   assign mks1[5] = 8; // is the logic any cheaper if this is a 6?
   assign mks1[6] = 8;
   assign mks1[7] = 8;
+
+  assign mks0[0] = -4;
+  assign mks0[1] = -4;
+  assign mks0[2] = -6;
+  assign mks0[3] = -6;
+  assign mks0[4] = -6;
+  assign mks0[5] = -8;
+  assign mks0[6] = -8;
+  assign mks0[7] = -8;
+  assign mksm1[0] = -13;
+  assign mksm1[1] = -14;
+  assign mksm1[2] = -16;
+  assign mksm1[3] = -17;
+  assign mksm1[4] = -18;
+  assign mksm1[5] = -20; 
+  assign mksm1[6] = -22;
+  assign mksm1[7] = -23;
+
   
   // handles special case when j = 0 or j = 1 for sqrt
   assign mkj2 = 20; // when j = 1 use mk2[101] when j = 0 use anything bigger than 7.
@@ -85,8 +103,13 @@ module fdivsqrtuslc4cmp (
   
   assign mk2 = sqrtspecial ? mkj2 : mks2[A];
   assign mk1 = sqrtspecial ? mkj1 : mks1[A];
+  assign mk0 = sqrtspecial ? -mkj1 : mks0[A];
+  assign mkm1 = sqrtspecial ? -mkj2 : mksm1[A];
+
+/* Nannarelli12 design to exploit symmetry is slower because of negation and mux for special case of A = 000
   assign mk0 = -mk1;
   assign mkm1 = (A == 3'b000) ? -13 : -mk2; // asymmetry in table *** can we hide from critical path
+  */
  
   // Compare residual W to selection constants to choose digit
   always_comb