diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv
index 2ddd13072..e5f215e07 100644
--- a/testbench/testbench-fp.sv
+++ b/testbench/testbench-fp.sv
@@ -644,11 +644,11 @@ module testbenchfp;
    // Read the first test
    initial begin
       //string testname = {`PATH, Tests[TestNum]}; 
-      string p = `PATH;
+      static string pp = `PATH;
       string testname;
       string tt0;
       tt0 = $psprintf("%s", Tests[TestNum]);
-      testname = {p, tt0};
+      testname = {pp, tt0};
       $display("Here you are %s", testname);     
       $display("\n\nRunning %s vectors ", Tests[TestNum]);
       $readmemh(testname, TestVectors);
diff --git a/testbench/testbench-imperas.sv b/testbench/testbench-imperas.sv
index 4360d4422..b503372d4 100644
--- a/testbench/testbench-imperas.sv
+++ b/testbench/testbench-imperas.sv
@@ -72,6 +72,7 @@ module testbench;
   logic             HMASTLOCK;
   logic             HCLK, HRESETn;
   logic [P.XLEN-1:0] PCW;
+  logic [31:0]      NextInstrE, InstrM;
 
   string ProgramAddrMapFile, ProgramLabelMapFile;
   integer   	ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
@@ -81,7 +82,8 @@ module testbench;
 
   logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
   logic        UARTSin, UARTSout;
-
+  logic        SPIIn, SPIOut;
+  logic [3:0]  SPICS;
   logic        SDCIntr;
 
   logic        HREADY;
@@ -255,7 +257,7 @@ module testbench;
   wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
                         .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
                         .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
-                        .UARTSin, .UARTSout, .SDCIntr); 
+                        .UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn); 
 
   // Track names of instructions
   instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
@@ -299,7 +301,6 @@ module testbench;
   end
 
   // Duplicate copy of pipeline registers that are optimized out of some configurations
-  logic [31:0] NextInstrE, InstrM;
   mux2    #(32)     FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE);
   flopenr #(32)     InstrMReg(clk, reset, ~dut.core.ifu.StallM, NextInstrE, InstrM);
 
diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv
index c5443af42..d38535003 100644
--- a/testbench/testbench-linux-imperas.sv
+++ b/testbench/testbench-linux-imperas.sv
@@ -282,7 +282,9 @@ module testbench;
   logic SDCCmdOE;
   logic [3:0] SDCDatIn;
   logic       SDCIntr;
-  
+  logic        SPIIn, SPIOut;
+  logic [3:0]  SPICS;
+
 
   // Hardwire UART, GPIO pins
   assign GPIOIN = 0;
@@ -440,13 +442,10 @@ module testbench;
   
 
   // Wally
-  wallypipelinedsoc #(P) dut(.clk, .reset, .reset_ext,
-                        .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HRESPEXT, .HCLK, 
-			.HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, 
-			.HTRANS, .HMASTLOCK, 
-			.TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN,
-                        .UARTSin, .UARTSout,
-			.SDCIntr);
+  wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
+                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+                        .UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn); 
 
   // W-stage hardware not needed by Wally itself 
   parameter nop = 'h13;
diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv
index ef165865f..011c4d148 100644
--- a/testbench/testbench-linux.sv
+++ b/testbench/testbench-linux.sv
@@ -258,6 +258,8 @@ module testbench;
   logic [31:0]      GPIOIN;
   logic [31:0]      GPIOOUT, GPIOEN;
   logic             UARTSin, UARTSout;
+  logic             SPIIn, SPIOut;
+  logic [3:0]       SPICS;
 
   // FPGA-specific Stuff
   logic             SDCIntr;
@@ -268,13 +270,10 @@ module testbench;
   assign SDCIntr = 0;
 
   // Wally
-  wallypipelinedsoc #(P) dut(.clk, .reset, .reset_ext,
-                        .HRDATAEXT, .HREADYEXT, .HREADY, .HSELEXT, .HSELEXTSDC, .HRESPEXT, .HCLK, 
-			.HRESETn, .HADDR, .HWDATA, .HWRITE, .HWSTRB, .HSIZE, .HBURST, .HPROT, 
-			.HTRANS, .HMASTLOCK, 
-			.TIMECLK('0), .GPIOIN, .GPIOOUT, .GPIOEN,
-                        .UARTSin, .UARTSout,
-			.SDCIntr);
+  wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
+                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+                        .UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn); 
 
   // W-stage hardware not needed by Wally itself 
   parameter nop = 'h13;
diff --git a/testbench/testbench-xcelium.sv b/testbench/testbench-xcelium.sv
index f5dd89290..44afbcd3b 100644
--- a/testbench/testbench-xcelium.sv
+++ b/testbench/testbench-xcelium.sv
@@ -70,6 +70,8 @@ module testbench;
   logic [3:0]  SDCDatIn;
   tri1  [3:0]  SDCDat;
   tri1         SDCCmd;
+  logic        SPIIn, SPIOut;
+  logic [3:0]  SPICS;
 
   logic        HREADY;
   logic        HSELEXT;
@@ -426,10 +428,10 @@ module testbench;
     assign SDCDat = '0;
   end
 
-  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
-    .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
-    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
-    .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+  wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
+                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+                        .UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn); 
 
   // generate clock to sequence tests
   always begin