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Bug fixes related to size of fpdivsqrt bit count and number of cycles

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This commit is contained in:
David Harris 2023-11-11 05:58:53 -08:00
parent 448ced00c5
commit 2bf5143163
3 changed files with 8 additions and 3 deletions
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4
config/shared/config-shared.vh
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@ -93,6 +93,7 @@ localparam NF2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_NF : H_NF);
localparam FMT2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? 2'd0 : 2'd2);
localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS);
// intermediate division parameters not directly used in Divider
localparam FPDIVN = NF+3; // length of floating-point inputs: Ns + 2 = Nf + 3 for 1 integer bit, Nf fracitonal bits, 2 extra bits to shift sqrt into [1/4, 1)]
localparam DIVN = ((FPDIVN<XLEN) & IDIV_ON_FPU) ? XLEN : FPDIVN; // standard length of input: max(XLEN, NF+2) ***
@ -101,10 +102,11 @@ localparam DIVN = ((FPDIVN<XLEN) & IDIV_ON_FPU) ? XLEN : FPDIVN; // stand
localparam LOGR = $clog2(RADIX); // r = log(R)
localparam RK = LOGR*DIVCOPIES; // r*k bits per cycle generated
localparam FPDUR = (DIVN+LOGR-1)/RK + 1 ; // ceiling((n+r)/rk)
localparam DURLEN = $clog2(FPDUR+1); // number of bits to represent the duration
localparam DIVb = FPDUR*RK - 1; // canonical fdiv size (b)
localparam DURLEN = $clog2(FPDUR+1);
localparam DIVBLEN = $clog2(DIVb+2)-1; // *** where is 2 coming from?
// largest length in IEU/FPU
localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF)); // max(XLEN, NF)
localparam LLEN = (($unsigned(FLEN)<$unsigned(XLEN)) ? ($unsigned(XLEN)) : ($unsigned(FLEN)));

2
src/fpu/fdivsqrt/fdivsqrtcycles.sv
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@ -34,7 +34,7 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
output logic [P.DURLEN-1:0] CyclesE
);
logic [P.DURLEN+1:0] Nf, FPResultBitsE; // number of fractional bits
logic [P.DIVBLEN:0] Nf, FPResultBitsE; // number of fractional bits
logic [P.DIVBLEN:0] ResultBitsE; // number of result bits;
// DIVN = P.NF+3

3
testbench/testbench-fp.sv
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@ -148,6 +148,9 @@ module testbenchfp;
$display("\nThe start of simulation...");
$display("This simulation for TEST is %s", TEST);
$display("This simulation for TEST is of the operand size of %s", TEST_SIZE);
$display("FPDUR %d %d DIVN %d LOGR %d RK %d RADIX %d DURLEN %d", FPDUR, DIVN, LOGR, RK, RADIX, DURLEN);
if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported
if (TEST === "cvtint" | TEST === "all") begin // if testing integer conversion
// add the 128-bit cvtint tests to the to-be-tested list