diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh
index 61bf461eb..cc230ef3e 100644
--- a/config/shared/config-shared.vh
+++ b/config/shared/config-shared.vh
@@ -93,6 +93,7 @@ localparam NF2   = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_NF   : H_NF);
 localparam FMT2  = ((F_SUPPORTED & (LEN1 != S_LEN)) ? 2'd0    : 2'd2);
 localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS);
 
+
 // intermediate division parameters not directly used in Divider
 localparam FPDIVN      = NF+3; // length of floating-point inputs: Ns + 2 = Nf + 3 for 1 integer bit, Nf fracitonal bits, 2 extra bits to shift sqrt into [1/4, 1)]
 localparam DIVN        = ((FPDIVN<XLEN) & IDIV_ON_FPU) ? XLEN : FPDIVN; // standard length of input: max(XLEN, NF+2) ***
@@ -101,10 +102,11 @@ localparam DIVN        = ((FPDIVN<XLEN) & IDIV_ON_FPU) ? XLEN : FPDIVN; // stand
 localparam LOGR        = $clog2(RADIX);                             // r = log(R)
 localparam RK          = LOGR*DIVCOPIES;                            // r*k bits per cycle generated
 localparam FPDUR       = (DIVN+LOGR-1)/RK + 1 ;                     // ceiling((n+r)/rk)
-localparam DURLEN      = $clog2(FPDUR+1);                           // number of bits to represent the duration
-localparam DIVb        = FPDUR*RK - 1; // canonical fdiv size (b)
+localparam DIVb        = FPDUR*RK - 1;                              // canonical fdiv size (b)
+localparam DURLEN      = $clog2(FPDUR+1);
 localparam DIVBLEN     = $clog2(DIVb+2)-1;                          // *** where is 2 coming from?
 
+
 // largest length in IEU/FPU
 localparam CVTLEN = ((NF<XLEN) ? (XLEN) : (NF));  // max(XLEN, NF)
 localparam LLEN = (($unsigned(FLEN)<$unsigned(XLEN)) ? ($unsigned(XLEN)) : ($unsigned(FLEN)));
diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv
index d5c571940..9d7f05fc8 100644
--- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv
@@ -34,7 +34,7 @@ module fdivsqrtcycles import cvw::*;  #(parameter cvw_t P) (
   output logic [P.DURLEN-1:0]  CyclesE
 );
 
-  logic [P.DURLEN+1:0] Nf, FPResultBitsE; // number of fractional bits
+  logic [P.DIVBLEN:0] Nf, FPResultBitsE; // number of fractional bits
   logic [P.DIVBLEN:0]  ResultBitsE; // number of result bits;
 
   // DIVN = P.NF+3
diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv
index 5ef752691..9e602cab0 100644
--- a/testbench/testbench-fp.sv
+++ b/testbench/testbench-fp.sv
@@ -148,6 +148,9 @@ module testbenchfp;
       $display("\nThe start of simulation...");      
       $display("This simulation for TEST is %s", TEST);
       $display("This simulation for TEST is of the operand size of %s", TEST_SIZE);      
+
+      $display("FPDUR %d %d DIVN %d LOGR %d RK %d RADIX %d DURLEN %d", FPDUR, DIVN, LOGR, RK, RADIX, DURLEN);
+
       if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported
 	 if (TEST === "cvtint" | TEST === "all") begin  // if testing integer conversion
             // add the 128-bit cvtint tests to the to-be-tested list