change where DPC is muxed into pipe

bin/hw_debug_test.py

@@ -169,5 +169,5 @@ with OpenOCD() as cvw:
     cvw.reset_hart()
     time.sleep(1)
     #register_rw_test(cvw)
-    #flow_control_test(cvw)
+    flow_control_test(cvw)
-    prog_buff_test(cvw)
+    #prog_buff_test(cvw)

src/debug/dmc.sv

@@ -103,8 +103,16 @@ module dmc (
         end
 
         HALTED : begin
-          if (ResumeReq)
+          if (ResumeReq) begin
-            State <= RESUME;
+            //State <= RESUME;
+            if (Step) begin
+              Counter <= E2M_CYCLE_COUNT;
+              State <= STEP;
+            end else begin
+              State <= RUNNING;
+              ResumeAck <= 1;
+            end
+          end
         end
 
         // Wait a cycle to load PCF from DPC before resuming

src/ifu/ifu.sv

@@ -99,8 +99,6 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   output logic                 ICacheMiss,                               // Report I$ miss to performance counters
   // Debug Mode logic
   output logic [P.XLEN-1:0]    PCNextF,                                  // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
-  input  logic                 ExitDebugMode,
-  input  logic [P.XLEN-1:0]    DPC,
   input  logic                 ProgBuffScanEn,
   // Debug scan chain
   input  logic [3:0]           ProgBufAddr,
@@ -337,14 +335,8 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
 
 
   mux3 #(P.XLEN) pcmux3(PC2NextF, EPCM, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
-
-  if (P.DEBUG_SUPPORTED) begin
-    mux3 #(P.XLEN) pcresetmux(.d2(P.RESET_VECTOR[P.XLEN-1:0]), .d1(DPC), .d0({UnalignedPCNextF[P.XLEN-1:1], 1'b0}), .s({reset,ExitDebugMode}), .y(PCNextF));
-    flopen #(P.XLEN) pcreg(clk, ~StallF | reset | ExitDebugMode, PCNextF, PCF);
-  end else begin
   mux2 #(P.XLEN) pcresetmux({UnalignedPCNextF[P.XLEN-1:1], 1'b0}, P.RESET_VECTOR[P.XLEN-1:0], reset, PCNextF);
   flopen #(P.XLEN) pcreg(clk, ~StallF | reset, PCNextF, PCF);
-  end
 
   // pcadder
   // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32

src/privileged/csr.sv

@@ -99,6 +99,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   output logic                     ebreakEn,
   output logic                     Step,
   output logic [P.XLEN-1:0]        DPC,
+  input  logic                     ExitDebugMode,
   input  logic                     EnterDebugMode,
   // Debug scan chain
   input  logic                     DebugSel,
@@ -184,7 +185,12 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   // Trap Returns
   // A trap sets the PC to TrapVector
   // A return sets the PC to MEPC or SEPC
+  if (P.DEBUG_SUPPORTED) begin
+    mux3 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, DPC, {ExitDebugMode,mretM}, EPCM);
+  end else begin
     mux2 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPCM);
+  end
+
 
   ///////////////////////////////////////////
   // CSRWriteValM

src/privileged/privileged.sv

@@ -106,6 +106,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   output logic              Step,
   output logic [P.XLEN-1:0] DPC,
   input  logic              EnterDebugMode,
+  input  logic              ExitDebugMode,
   // Debug scan chain
   input  logic              DebugSel,
   input  logic [11:0]       DebugRegAddr,
@@ -165,7 +166,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
     .SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE,
     .EPCM, .TrapVectorM,
     .CSRReadValW, .IllegalCSRAccessM, .BigEndianM,
-    .DebugMode, .DebugCause, .ebreakEn, .Step, .DPC, .EnterDebugMode,
+    .DebugMode, .DebugCause, .ebreakEn, .Step, .DPC, .EnterDebugMode, .ExitDebugMode,
     .DebugSel, .DebugRegAddr, .DebugCapture, .DebugRegUpdate, .DebugScanEn, .DebugScanIn, .DebugScanOut);
 
   // pipeline early-arriving trap sources

src/wally/wallypipelinedcore.sv

@@ -227,7 +227,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
     .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
     // pmp/pma (inside mmu) signals. 
     .PMPCFG_ARRAY_REGW,  .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrUpdateDAF,
-    .ExitDebugMode, .DPC, .PCNextF, .ProgBuffScanEn, .ProgBufAddr, .ProgBufScanIn(DebugScanIn),
+    .PCNextF, .ProgBuffScanEn, .ProgBufAddr, .ProgBufScanIn(DebugScanIn),
     .DebugScanEn(DebugScanEn & MiscSel), .DebugScanIn(DebugScanReg[0]), .DebugScanOut(DebugScanReg[1]));
     
   // integer execution unit: integer register file, datapath and controller
@@ -355,7 +355,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, 
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
       .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM, .ebreakM,
-      .ebreakEn, .ForceBreakPoint, .DebugMode, .DebugCause, .Step, .DPC, .EnterDebugMode,
+      .ebreakEn, .ForceBreakPoint, .DebugMode, .DebugCause, .Step, .DPC, .EnterDebugMode, .ExitDebugMode,
       .DebugSel(CSRSel), .DebugRegAddr, .DebugCapture, .DebugRegUpdate, .DebugScanEn(DebugScanEn & CSRSel), .DebugScanIn, .DebugScanOut(CSRScanOut));
     if (P.DEBUG_SUPPORTED) begin
       flopenrs #(1) scantrapm (.clk, .reset, .en(DebugCapture), .d(TrapM), .q(), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DebugScanReg[0]));