diff --git a/bin/hw_debug_test.py b/bin/hw_debug_test.py index 8cc59f96f..8a711157b 100755 --- a/bin/hw_debug_test.py +++ b/bin/hw_debug_test.py @@ -169,5 +169,5 @@ with OpenOCD() as cvw: cvw.reset_hart() time.sleep(1) #register_rw_test(cvw) - #flow_control_test(cvw) - prog_buff_test(cvw) + flow_control_test(cvw) + #prog_buff_test(cvw) diff --git a/src/debug/dmc.sv b/src/debug/dmc.sv index c7e792ae9..b2324e393 100644 --- a/src/debug/dmc.sv +++ b/src/debug/dmc.sv @@ -103,8 +103,16 @@ module dmc ( end HALTED : begin - if (ResumeReq) - State <= RESUME; + if (ResumeReq) begin + //State <= RESUME; + if (Step) begin + Counter <= E2M_CYCLE_COUNT; + State <= STEP; + end else begin + State <= RUNNING; + ResumeAck <= 1; + end + end end // Wait a cycle to load PCF from DPC before resuming diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 9ba4fd5c9..8bfd7e846 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -99,8 +99,6 @@ module ifu import cvw::*; #(parameter cvw_t P) ( output logic ICacheMiss, // Report I$ miss to performance counters // Debug Mode logic output logic [P.XLEN-1:0] PCNextF, // Next PCF, selected from Branch predictor, Privilege, or PC+2/4 - input logic ExitDebugMode, - input logic [P.XLEN-1:0] DPC, input logic ProgBuffScanEn, // Debug scan chain input logic [3:0] ProgBufAddr, @@ -337,14 +335,8 @@ module ifu import cvw::*; #(parameter cvw_t P) ( mux3 #(P.XLEN) pcmux3(PC2NextF, EPCM, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF); - - if (P.DEBUG_SUPPORTED) begin - mux3 #(P.XLEN) pcresetmux(.d2(P.RESET_VECTOR[P.XLEN-1:0]), .d1(DPC), .d0({UnalignedPCNextF[P.XLEN-1:1], 1'b0}), .s({reset,ExitDebugMode}), .y(PCNextF)); - flopen #(P.XLEN) pcreg(clk, ~StallF | reset | ExitDebugMode, PCNextF, PCF); - end else begin - mux2 #(P.XLEN) pcresetmux({UnalignedPCNextF[P.XLEN-1:1], 1'b0}, P.RESET_VECTOR[P.XLEN-1:0], reset, PCNextF); - flopen #(P.XLEN) pcreg(clk, ~StallF | reset, PCNextF, PCF); - end + mux2 #(P.XLEN) pcresetmux({UnalignedPCNextF[P.XLEN-1:1], 1'b0}, P.RESET_VECTOR[P.XLEN-1:0], reset, PCNextF); + flopen #(P.XLEN) pcreg(clk, ~StallF | reset, PCNextF, PCF); // pcadder // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32 diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 48cd38268..57f9500d2 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -99,6 +99,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( output logic ebreakEn, output logic Step, output logic [P.XLEN-1:0] DPC, + input logic ExitDebugMode, input logic EnterDebugMode, // Debug scan chain input logic DebugSel, @@ -184,7 +185,12 @@ module csr import cvw::*; #(parameter cvw_t P) ( // Trap Returns // A trap sets the PC to TrapVector // A return sets the PC to MEPC or SEPC - mux2 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPCM); + if (P.DEBUG_SUPPORTED) begin + mux3 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, DPC, {ExitDebugMode,mretM}, EPCM); + end else begin + mux2 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPCM); + end + /////////////////////////////////////////// // CSRWriteValM diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 0aa23be7f..ffb9f3d86 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -106,6 +106,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( output logic Step, output logic [P.XLEN-1:0] DPC, input logic EnterDebugMode, + input logic ExitDebugMode, // Debug scan chain input logic DebugSel, input logic [11:0] DebugRegAddr, @@ -165,7 +166,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( .SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .EPCM, .TrapVectorM, .CSRReadValW, .IllegalCSRAccessM, .BigEndianM, - .DebugMode, .DebugCause, .ebreakEn, .Step, .DPC, .EnterDebugMode, + .DebugMode, .DebugCause, .ebreakEn, .Step, .DPC, .EnterDebugMode, .ExitDebugMode, .DebugSel, .DebugRegAddr, .DebugCapture, .DebugRegUpdate, .DebugScanEn, .DebugScanIn, .DebugScanOut); // pipeline early-arriving trap sources diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index ee6ec1d08..88ead28b4 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -227,7 +227,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, .ITLBWriteF, .sfencevmaM, .ITLBMissF, // pmp/pma (inside mmu) signals. .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrUpdateDAF, - .ExitDebugMode, .DPC, .PCNextF, .ProgBuffScanEn, .ProgBufAddr, .ProgBufScanIn(DebugScanIn), + .PCNextF, .ProgBuffScanEn, .ProgBufAddr, .ProgBufScanIn(DebugScanIn), .DebugScanEn(DebugScanEn & MiscSel), .DebugScanIn(DebugScanReg[0]), .DebugScanOut(DebugScanReg[1])); // integer execution unit: integer register file, datapath and controller @@ -355,7 +355,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM, .ebreakM, - .ebreakEn, .ForceBreakPoint, .DebugMode, .DebugCause, .Step, .DPC, .EnterDebugMode, + .ebreakEn, .ForceBreakPoint, .DebugMode, .DebugCause, .Step, .DPC, .EnterDebugMode, .ExitDebugMode, .DebugSel(CSRSel), .DebugRegAddr, .DebugCapture, .DebugRegUpdate, .DebugScanEn(DebugScanEn & CSRSel), .DebugScanIn, .DebugScanOut(CSRScanOut)); if (P.DEBUG_SUPPORTED) begin flopenrs #(1) scantrapm (.clk, .reset, .en(DebugCapture), .d(TrapM), .q(), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DebugScanReg[0]));