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Fixed lint errors, presumably detected by latest version of verilator

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David Harris 2023-06-11 06:48:42 -07:00
parent 99fe09fb40
commit 29b48334d8
2 changed files with 5 additions and 4 deletions
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1
src/fpu/fdivsqrt/fdivsqrtcycles.sv
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@ -53,6 +53,7 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
P.FMT: Nf = P.NF; P.FMT: Nf = P.NF;
P.FMT1: Nf = P.NF1; P.FMT1: Nf = P.NF1;
P.FMT2: Nf = P.NF2; P.FMT2: Nf = P.NF2;
default: Nf = 'x; // shouldn't happen
endcase endcase
else if (P.FPSIZES == 4) else if (P.FPSIZES == 4)
always_comb always_comb

2
src/fpu/postproc/cvtshiftcalc.sv
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@ -82,7 +82,7 @@ module cvtshiftcalc import cvw::*; #(parameter cvw_t P) (
P.FMT: ResNegNF = -($clog2(P.NF)+1)'(P.NF); P.FMT: ResNegNF = -($clog2(P.NF)+1)'(P.NF);
P.FMT1: ResNegNF = -($clog2(P.NF)+1)'(P.NF1); P.FMT1: ResNegNF = -($clog2(P.NF)+1)'(P.NF1);
P.FMT2: ResNegNF = -($clog2(P.NF)+1)'(P.NF2); P.FMT2: ResNegNF = -($clog2(P.NF)+1)'(P.NF2);
default: ResNegNF = 1'bx; default: ResNegNF = 'x;
endcase endcase
end else if (P.FPSIZES == 4) begin end else if (P.FPSIZES == 4) begin