diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv
index ea89ce7c6..c7aea4588 100644
--- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv
@@ -50,9 +50,10 @@ module fdivsqrtcycles import cvw::*;  #(parameter cvw_t P) (
   else if (P.FPSIZES == 3)
     always_comb
       case (FmtE)
-        P.FMT:  Nf = P.NF;
-        P.FMT1: Nf = P.NF1;
-        P.FMT2: Nf = P.NF2; 
+        P.FMT:   Nf = P.NF;
+        P.FMT1:  Nf = P.NF1;
+        P.FMT2:  Nf = P.NF2; 
+        default: Nf = 'x; // shouldn't happen
       endcase
   else if (P.FPSIZES == 4)  
     always_comb
diff --git a/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv
index 105778d0c..2cc42e54d 100644
--- a/src/fpu/postproc/cvtshiftcalc.sv
+++ b/src/fpu/postproc/cvtshiftcalc.sv
@@ -82,7 +82,7 @@ module cvtshiftcalc import cvw::*;  #(parameter cvw_t P) (
               P.FMT:  ResNegNF = -($clog2(P.NF)+1)'(P.NF);
               P.FMT1: ResNegNF = -($clog2(P.NF)+1)'(P.NF1);
               P.FMT2: ResNegNF = -($clog2(P.NF)+1)'(P.NF2);
-              default: ResNegNF = 1'bx;
+              default: ResNegNF = 'x;
           endcase
 
   end else if (P.FPSIZES == 4) begin