From 29634f1475ffaa8d9984f00f096bde66033fb1e3 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Wed, 17 Mar 2021 15:16:01 -0500 Subject: [PATCH] Temporarily reverted my last few commits --- wally-pipelined/regression/wally-pipelined.do | 2 +- wally-pipelined/testbench/testbench-coremark_bare.sv | 11 ++--------- 2 files changed, 3 insertions(+), 10 deletions(-) diff --git a/wally-pipelined/regression/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do index 5f3b0d710..cabcfe153 100644 --- a/wally-pipelined/regression/wally-pipelined.do +++ b/wally-pipelined/regression/wally-pipelined.do @@ -30,7 +30,7 @@ vlib work # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined.do ../config/rv32ic switch $argc { - 0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583} + 0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583} 1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583} } # start and run simulation diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index f3bb22f88..d0ac7f286 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -34,7 +34,6 @@ module testbench(); string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [`XLEN-1:0] meminit; string tests[]; - string ProgramAddrMapFile, ProgramLabelMapFile; logic [`AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; logic [31:0] HADDR; @@ -77,8 +76,8 @@ module testbench(); $readmemh(memfilename, dut.uncore.dtim.RAM); for(j=2371; j < 65535; j = j+1) dut.uncore.dtim.RAM[j] = 64'b0; - ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr"; - ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab"; +// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr"; +// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab"; reset = 1; # 22; reset = 0; end // generate clock to sequence tests @@ -95,12 +94,6 @@ module testbench(); end end - if (1 == 1) begin : functionRadix - function_radix function_radix(.reset(reset), - .ProgramAddrMapFile(ProgramAddrMapFile), - .ProgramLabelMapFile(ProgramLabelMapFile)); - end - initial begin $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory); $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);