mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
No longer forcing CSRReadValM because that can feedback to corrupt some CSRs
This commit is contained in:
bbracker
parent
0646bf2b90
commit
28fed18421
@ -33,6 +33,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -divider M
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add wave -noupdate -divider M
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCM
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCM
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add wave -noupdate /testbench/InstrMName
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add wave -noupdate /testbench/InstrMName
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add wave -noupdate /testbench/textM
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrM
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidM
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidM
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/lsu/dcache/MemPAdrM
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/lsu/dcache/MemPAdrM
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@ -114,77 +115,76 @@ add wave -noupdate -group EBU /testbench/dut/hart/ebu/NextBusState
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add wave -noupdate -divider W
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add wave -noupdate -divider W
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add wave -noupdate -radix hexadecimal /testbench/PCW
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add wave -noupdate -radix hexadecimal /testbench/PCW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidW
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add wave -noupdate /testbench/textM
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add wave -noupdate /testbench/dut/hart/ieu/dp/ReadDataW
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add wave -noupdate /testbench/dut/hart/ieu/dp/ReadDataW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -divider RegFile
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add wave -noupdate -group RF /testbench/dut/hart/ieu/dp/RegWriteW
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add wave -noupdate /testbench/dut/hart/ieu/dp/RegWriteW
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add wave -noupdate -group RF -radix unsigned /testbench/dut/hart/ieu/dp/RdW
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add wave -noupdate -radix unsigned /testbench/dut/hart/ieu/dp/RdW
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add wave -noupdate -group RF /testbench/dut/hart/ieu/dp/regf/wd3
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add wave -noupdate /testbench/dut/hart/ieu/dp/regf/wd3
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[2]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[2]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[3]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[3]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[4]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[4]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[5]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[5]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[6]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[6]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[7]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[7]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[8]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[8]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[9]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[9]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[10]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[10]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[11]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[11]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[12]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[12]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[13]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[13]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[14]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[14]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[15]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[15]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[16]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[16]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[17]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[17]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[18]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[18]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[19]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[19]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[20]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[20]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[21]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[21]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[22]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[22]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[23]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[23]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[24]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[24]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[25]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[25]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[26]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[26]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[27]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[27]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[28]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[28]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[29]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[29]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[30]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[30]}
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add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[31]}
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add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[31]}
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/MSTATUS_REGW
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add wave -noupdate -divider CSRs
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTINHIBIT_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MSTATUS_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTEREN_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTINHIBIT_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIDELEG_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTEREN_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIP_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIDELEG_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIE_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIP_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIE_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVEC_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTEREN_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVEC_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTEREN_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCH_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCH_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/SSTATUS_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/SCOUNTEREN_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SSTATUS_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIP_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SCOUNTEREN_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIE_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIP_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIE_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/STVEC_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SCOUNTEREN_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/STVEC_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEDELEG_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SCOUNTEREN_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SIDELEG_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEDELEG_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SATP_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SIDELEG_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/USTATUS_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SATP_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UEPC_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/USTATUS_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UTVEC_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UEPC_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIP_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UTVEC_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIE_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIP_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG_ARRAY_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIE_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG_ARRAY_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MISA_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW
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add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/FRM_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MISA_REGW
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add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/FRM_REGW
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add wave -noupdate -divider <NULL>
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add wave -noupdate -divider <NULL>
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add wave -hex -r /testbench/*
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add wave -hex -r /testbench/*
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TreeUpdate [SetDefaultTree]
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TreeUpdate [SetDefaultTree]
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@ -265,13 +265,13 @@ module testbench();
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end
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end
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// override on special conditions
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// override on special conditions
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if (ExpectedMemAdrM == 'h10000005) begin
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if (ExpectedMemAdrM == 'h10000005) begin
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//$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW);
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//$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW);
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force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM;
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force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM;
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end
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end
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if(textM.substr(0,5) == "rdtime") begin
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if(textM.substr(0,5) == "rdtime") begin
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$display("%tns, %d instrs: Overwrite read value of CSR on read of MTIME in memory stage.", $time, InstrCountW);
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$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW);
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force dut.hart.priv.csr.CSRReadValM = ExpectedRegValueM;
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force dut.uncore.clint.clint.MTIME = ExpectedRegValueM;
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//dut.hart.ieu.dp.regf.wd3
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//dut.hart.ieu.dp.regf.wd3
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end
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end
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end // if (checkInstrM)
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end // if (checkInstrM)
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@ -291,74 +291,73 @@ module testbench();
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ExpectedMemWriteDataW <= '0;
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ExpectedMemWriteDataW <= '0;
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ExpectedMemReadDataW <= '0;
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ExpectedMemReadDataW <= '0;
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NumCSRW <= '0;
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NumCSRW <= '0;
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end
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end else if(~dut.hart.StallW) begin
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else if(~dut.hart.StallW) begin
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if(dut.hart.FlushW) begin
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if(dut.hart.FlushW) begin
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ExpectedPCW <= '0;
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ExpectedPCW <= '0;
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ExpectedInstrW <= '0;
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ExpectedInstrW <= '0;
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textW <= "";
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textW <= "";
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RegWriteW <= "";
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RegWriteW <= "";
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ExpectedRegAdrW <= '0;
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ExpectedRegAdrW <= '0;
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ExpectedRegValueW <= '0;
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ExpectedRegValueW <= '0;
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ExpectedMemAdrW <= '0;
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ExpectedMemAdrW <= '0;
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MemOpW <= "";
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MemOpW <= "";
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ExpectedMemWriteDataW <= '0;
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ExpectedMemWriteDataW <= '0;
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ExpectedMemReadDataW <= '0;
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ExpectedMemReadDataW <= '0;
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NumCSRW <= '0;
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NumCSRW <= '0;
|
||||||
end else begin
|
end else begin
|
||||||
ExpectedPCW <= ExpectedPCM;
|
ExpectedPCW <= ExpectedPCM;
|
||||||
ExpectedInstrW <= ExpectedInstrM;
|
ExpectedInstrW <= ExpectedInstrM;
|
||||||
textW <= textM;
|
textW <= textM;
|
||||||
RegWriteW <= RegWriteM;
|
RegWriteW <= RegWriteM;
|
||||||
ExpectedRegAdrW <= ExpectedRegAdrM;
|
ExpectedRegAdrW <= ExpectedRegAdrM;
|
||||||
ExpectedRegValueW <= ExpectedRegValueM;
|
ExpectedRegValueW <= ExpectedRegValueM;
|
||||||
ExpectedMemAdrW <= ExpectedMemAdrM;
|
ExpectedMemAdrW <= ExpectedMemAdrM;
|
||||||
MemOpW <= MemOpM;
|
MemOpW <= MemOpM;
|
||||||
ExpectedMemWriteDataW <= ExpectedMemWriteDataM;
|
ExpectedMemWriteDataW <= ExpectedMemWriteDataM;
|
||||||
ExpectedMemReadDataW <= ExpectedMemReadDataM;
|
ExpectedMemReadDataW <= ExpectedMemReadDataM;
|
||||||
NumCSRW <= NumCSRM;
|
NumCSRW <= NumCSRM;
|
||||||
for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin
|
for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin
|
||||||
ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex];
|
ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex];
|
||||||
ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex];
|
ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex];
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
// override on special conditions
|
// override on special conditions
|
||||||
#1;
|
#1;
|
||||||
|
|
||||||
|
|
||||||
if(~dut.hart.StallW) begin
|
if(~dut.hart.StallW) begin
|
||||||
if(textM.substr(0,5) == "rdtime") begin
|
if(textW.substr(0,5) == "rdtime") begin
|
||||||
$display("%tns, %d instrs: Releasing force of CSRReadValM.", $time, InstrCountW);
|
$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
|
||||||
release dut.hart.priv.csr.CSRReadValM;
|
release dut.uncore.clint.clint.MTIME;
|
||||||
//release dut.hart.ieu.dp.regf.wd3;
|
//release dut.hart.ieu.dp.regf.wd3;
|
||||||
end
|
end
|
||||||
|
|
||||||
if (ExpectedMemAdrM == 'h10000005) begin
|
|
||||||
//$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW);
|
|
||||||
release dut.hart.ieu.dp.ReadDataM;
|
|
||||||
end
|
|
||||||
|
|
||||||
// force interrupts to 0
|
|
||||||
for(NumCSRMIndex = 0; NumCSRMIndex < NumCSRM; NumCSRMIndex++) begin
|
|
||||||
if(ExpectedCSRArrayM[NumCSRMIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRMIndex][`XLEN-1] == 1'b1)) begin
|
|
||||||
//what type?
|
|
||||||
ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C;
|
|
||||||
$display("%tns, %d instrs: CSR = %s. Forcing interrupt of cause = %x back to 0", $time, InstrCountW, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]);
|
|
||||||
|
|
||||||
if(ExpectedIntType == 0) begin
|
if (ExpectedMemAdrM == 'h10000005) begin
|
||||||
force dut.hart.priv.SwIntM = 1'b0;
|
//$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW);
|
||||||
$display("Force SwIntM");
|
release dut.hart.ieu.dp.ReadDataM;
|
||||||
end
|
end
|
||||||
else if(ExpectedIntType == 4) begin
|
|
||||||
force dut.hart.priv.TimerIntM = 1'b0;
|
// force interrupts to 0
|
||||||
$display("Force TimeIntM");
|
for(NumCSRMIndex = 0; NumCSRMIndex < NumCSRM; NumCSRMIndex++) begin
|
||||||
end
|
if(ExpectedCSRArrayM[NumCSRMIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRMIndex][`XLEN-1] == 1'b1)) begin
|
||||||
else if(ExpectedIntType == 8) begin
|
//what type?
|
||||||
force dut.hart.priv.ExtIntM = 1'b0;
|
ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C;
|
||||||
$display("Force ExtIntM");
|
$display("%tns, %d instrs: CSR = %s. Forcing interrupt of cause = %x back to 0", $time, InstrCountW, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]);
|
||||||
|
|
||||||
|
if(ExpectedIntType == 0) begin
|
||||||
|
force dut.hart.priv.SwIntM = 1'b0;
|
||||||
|
$display("Force SwIntM");
|
||||||
end
|
end
|
||||||
end
|
else if(ExpectedIntType == 4) begin
|
||||||
end
|
force dut.hart.priv.TimerIntM = 1'b0;
|
||||||
|
$display("Force TimeIntM");
|
||||||
|
end
|
||||||
|
else if(ExpectedIntType == 8) begin
|
||||||
|
force dut.hart.priv.ExtIntM = 1'b0;
|
||||||
|
$display("Force ExtIntM");
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user