From 28fed18421b6d91293678de60d5fb470e881f155 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 6 Sep 2021 22:59:54 -0400 Subject: [PATCH] No longer forcing CSRReadValM because that can feedback to corrupt some CSRs --- .../regression/wave-dos/linux-waves.do | 138 +++++++++--------- wally-pipelined/testbench/testbench-linux.sv | 119 ++++++++------- 2 files changed, 128 insertions(+), 129 deletions(-) diff --git a/wally-pipelined/regression/wave-dos/linux-waves.do b/wally-pipelined/regression/wave-dos/linux-waves.do index ce8b7a5b0..efb446a05 100644 --- a/wally-pipelined/regression/wave-dos/linux-waves.do +++ b/wally-pipelined/regression/wave-dos/linux-waves.do @@ -33,6 +33,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultE add wave -noupdate -divider M add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCM add wave -noupdate /testbench/InstrMName +add wave -noupdate /testbench/textM add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/InstrM add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidM add wave -noupdate -radix hexadecimal /testbench/dut/hart/lsu/dcache/MemPAdrM @@ -114,77 +115,76 @@ add wave -noupdate -group EBU /testbench/dut/hart/ebu/NextBusState add wave -noupdate -divider W add wave -noupdate -radix hexadecimal /testbench/PCW add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/c/InstrValidW +add wave -noupdate /testbench/textM add wave -noupdate /testbench/dut/hart/ieu/dp/ReadDataW add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -divider RegFile -add wave -noupdate /testbench/dut/hart/ieu/dp/RegWriteW -add wave -noupdate -radix unsigned /testbench/dut/hart/ieu/dp/RdW -add wave -noupdate /testbench/dut/hart/ieu/dp/regf/wd3 -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[2]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[3]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[4]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[5]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[6]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[7]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[8]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[9]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[10]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[11]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[12]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[13]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[14]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[15]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[16]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[17]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[18]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[19]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[20]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[21]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[22]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[23]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[24]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[25]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[26]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[27]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[28]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[29]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[30]} -add wave -noupdate -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[31]} -add wave -noupdate -divider CSRs -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MSTATUS_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTINHIBIT_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTEREN_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTEREN_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCH_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SSTATUS_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/SCOUNTEREN_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/STVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SCOUNTEREN_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SIDELEG_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SATP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/USTATUS_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UEPC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UTVEC_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIP_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIE_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG_ARRAY_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MISA_REGW -add wave -noupdate -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/FRM_REGW +add wave -noupdate -group RF /testbench/dut/hart/ieu/dp/RegWriteW +add wave -noupdate -group RF -radix unsigned /testbench/dut/hart/ieu/dp/RdW +add wave -noupdate -group RF /testbench/dut/hart/ieu/dp/regf/wd3 +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[2]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[3]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[4]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[5]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[6]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[7]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[8]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[9]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[10]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[11]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[12]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[13]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[14]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[15]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[16]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[17]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[18]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[19]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[20]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[21]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[22]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[23]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[24]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[25]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[26]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[27]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[28]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[29]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[30]} +add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/hart/ieu/dp/regf/rf[31]} +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/MSTATUS_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTINHIBIT_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/MCOUNTEREN_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIDELEG_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIP_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/MIE_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVEC_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTEREN_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MSCRATCH_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/SSTATUS_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/SCOUNTEREN_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIP_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csri/SIE_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/STVEC_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SCOUNTEREN_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SEDELEG_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SIDELEG_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrs/SATP_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/USTATUS_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UEPC_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UTVEC_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIP_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrn/UIE_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPCFG_ARRAY_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csrm/MISA_REGW +add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/hart/priv/csr/genblk1/csru/FRM_REGW add wave -noupdate -divider add wave -hex -r /testbench/* TreeUpdate [SetDefaultTree] diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index 15170840a..7eb1d224d 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -265,13 +265,13 @@ module testbench(); end // override on special conditions if (ExpectedMemAdrM == 'h10000005) begin - //$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW); + //$display("%tns, %d instrs: Overwriting read data from CLINT.", $time, InstrCountW); force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; end if(textM.substr(0,5) == "rdtime") begin - $display("%tns, %d instrs: Overwrite read value of CSR on read of MTIME in memory stage.", $time, InstrCountW); - force dut.hart.priv.csr.CSRReadValM = ExpectedRegValueM; - //dut.hart.ieu.dp.regf.wd3 + $display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW); + force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; + //dut.hart.ieu.dp.regf.wd3 end end // if (checkInstrM) @@ -291,74 +291,73 @@ module testbench(); ExpectedMemWriteDataW <= '0; ExpectedMemReadDataW <= '0; NumCSRW <= '0; - end - else if(~dut.hart.StallW) begin + end else if(~dut.hart.StallW) begin if(dut.hart.FlushW) begin - ExpectedPCW <= '0; - ExpectedInstrW <= '0; - textW <= ""; - RegWriteW <= ""; - ExpectedRegAdrW <= '0; - ExpectedRegValueW <= '0; - ExpectedMemAdrW <= '0; - MemOpW <= ""; - ExpectedMemWriteDataW <= '0; - ExpectedMemReadDataW <= '0; - NumCSRW <= '0; + ExpectedPCW <= '0; + ExpectedInstrW <= '0; + textW <= ""; + RegWriteW <= ""; + ExpectedRegAdrW <= '0; + ExpectedRegValueW <= '0; + ExpectedMemAdrW <= '0; + MemOpW <= ""; + ExpectedMemWriteDataW <= '0; + ExpectedMemReadDataW <= '0; + NumCSRW <= '0; end else begin - ExpectedPCW <= ExpectedPCM; - ExpectedInstrW <= ExpectedInstrM; - textW <= textM; - RegWriteW <= RegWriteM; - ExpectedRegAdrW <= ExpectedRegAdrM; - ExpectedRegValueW <= ExpectedRegValueM; - ExpectedMemAdrW <= ExpectedMemAdrM; - MemOpW <= MemOpM; - ExpectedMemWriteDataW <= ExpectedMemWriteDataM; - ExpectedMemReadDataW <= ExpectedMemReadDataM; - NumCSRW <= NumCSRM; - for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin - ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex]; - ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex]; - end + ExpectedPCW <= ExpectedPCM; + ExpectedInstrW <= ExpectedInstrM; + textW <= textM; + RegWriteW <= RegWriteM; + ExpectedRegAdrW <= ExpectedRegAdrM; + ExpectedRegValueW <= ExpectedRegValueM; + ExpectedMemAdrW <= ExpectedMemAdrM; + MemOpW <= MemOpM; + ExpectedMemWriteDataW <= ExpectedMemWriteDataM; + ExpectedMemReadDataW <= ExpectedMemReadDataM; + NumCSRW <= NumCSRM; + for(NumCSRWIndex = 0; NumCSRWIndex < NumCSRM; NumCSRWIndex++) begin + ExpectedCSRArrayW[NumCSRWIndex] = ExpectedCSRArrayM[NumCSRWIndex]; + ExpectedCSRArrayValueW[NumCSRWIndex] = ExpectedCSRArrayValueM[NumCSRWIndex]; + end end // override on special conditions #1; if(~dut.hart.StallW) begin - if(textM.substr(0,5) == "rdtime") begin - $display("%tns, %d instrs: Releasing force of CSRReadValM.", $time, InstrCountW); - release dut.hart.priv.csr.CSRReadValM; + if(textW.substr(0,5) == "rdtime") begin + $display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW); + release dut.uncore.clint.clint.MTIME; //release dut.hart.ieu.dp.regf.wd3; - end - - if (ExpectedMemAdrM == 'h10000005) begin - //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW); - release dut.hart.ieu.dp.ReadDataM; - end - - // force interrupts to 0 - for(NumCSRMIndex = 0; NumCSRMIndex < NumCSRM; NumCSRMIndex++) begin - if(ExpectedCSRArrayM[NumCSRMIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRMIndex][`XLEN-1] == 1'b1)) begin - //what type? - ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C; - $display("%tns, %d instrs: CSR = %s. Forcing interrupt of cause = %x back to 0", $time, InstrCountW, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]); + end - if(ExpectedIntType == 0) begin - force dut.hart.priv.SwIntM = 1'b0; - $display("Force SwIntM"); + if (ExpectedMemAdrM == 'h10000005) begin + //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW); + release dut.hart.ieu.dp.ReadDataM; end - else if(ExpectedIntType == 4) begin - force dut.hart.priv.TimerIntM = 1'b0; - $display("Force TimeIntM"); - end - else if(ExpectedIntType == 8) begin - force dut.hart.priv.ExtIntM = 1'b0; - $display("Force ExtIntM"); + + // force interrupts to 0 + for(NumCSRMIndex = 0; NumCSRMIndex < NumCSRM; NumCSRMIndex++) begin + if(ExpectedCSRArrayM[NumCSRMIndex].substr(1, 5) == "cause" && (ExpectedCSRArrayValueM[NumCSRMIndex][`XLEN-1] == 1'b1)) begin + //what type? + ExpectedIntType = ExpectedCSRArrayValueM[NumCSRM] & 64'h0000_000C; + $display("%tns, %d instrs: CSR = %s. Forcing interrupt of cause = %x back to 0", $time, InstrCountW, ExpectedCSRArrayM[NumCSRM], ExpectedCSRArrayValueM[NumCSRM]); + + if(ExpectedIntType == 0) begin + force dut.hart.priv.SwIntM = 1'b0; + $display("Force SwIntM"); end - end - end + else if(ExpectedIntType == 4) begin + force dut.hart.priv.TimerIntM = 1'b0; + $display("Force TimeIntM"); + end + else if(ExpectedIntType == 8) begin + force dut.hart.priv.ExtIntM = 1'b0; + $display("Force ExtIntM"); + end + end + end end end end