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Shared ALU mux input for shifts
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@ -69,13 +69,12 @@ module alu #(parameter WIDTH=32) (
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// Select appropriate ALU Result
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assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
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always_comb
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case (ALUFunct)
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casez (ALUFunct)
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3'b000: FullResult = Sum; // add or sub
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3'b001: FullResult = Shift; // sll
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3'b?01: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = SLT; // slt
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3'b011: FullResult = SLTU; // sltu
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3'b100: FullResult = A ^ B; // xor
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3'b101: FullResult = Shift; // sra or srl
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3'b110: FullResult = A | B; // or
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3'b111: FullResult = A & B; // and
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endcase
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@ -27,20 +27,16 @@
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module shifter (
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input logic [`XLEN-1:0] a,
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input logic [5:0] amt,
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input logic [`LOG_XLEN-1:0] amt,
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input logic right, arith, w64,
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output logic [`XLEN-1:0] y);
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localparam BITS = $clog2(`XLEN);
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logic [2*`XLEN-2:0] z, zshift;
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logic [BITS-1:0] amttrunc, offset;
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logic [`LOG_XLEN-1:0] amttrunc, offset;
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// The best shifter architecture differs based on `XLEN.
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// for RV32, only 32-bit shifts are needed. These are
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// most efficiently implemented with a funnel shifter.
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// For RV64, 32 and 64-bit shifts are needed, with sign
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// extension.
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// Handle left and right shifts with a funnel shifter.
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// For RV32, only 32-bit shifts are needed.
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// For RV64, 32 and 64-bit shifts are needed, with sign extension.
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// funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
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generate
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@ -50,7 +46,7 @@ module shifter (
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if (arith) z = {{31{a[31]}}, a};
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else z = {31'b0, a};
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else z = {a, 31'b0};
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assign amttrunc = amt[4:0]; // shift amount
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assign amttrunc = amt; // shift amount
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end else begin:shifter // RV64
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always_comb // funnel mux
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if (w64) begin // 32-bit shifts
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@ -64,7 +60,7 @@ module shifter (
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else z = {63'b0, a};
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else z = {a, 63'b0};
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end
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assign amttrunc = w64 ? {1'b0, amt[4:0]} : amt[5:0]; // 32 or 64-bit shift
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assign amttrunc = w64 ? {1'b0, amt[4:0]} : amt; // 32 or 64-bit shift
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end
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endgenerate
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