Shared ALU mux input for shifts

This commit is contained in:
David Harris 2021-12-18 10:08:52 -08:00
parent eed2765033
commit 27ec8ff893
2 changed files with 9 additions and 14 deletions

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@ -69,13 +69,12 @@ module alu #(parameter WIDTH=32) (
// Select appropriate ALU Result // Select appropriate ALU Result
assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0 assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
always_comb always_comb
case (ALUFunct) casez (ALUFunct)
3'b000: FullResult = Sum; // add or sub 3'b000: FullResult = Sum; // add or sub
3'b001: FullResult = Shift; // sll 3'b?01: FullResult = Shift; // sll, sra, or srl
3'b010: FullResult = SLT; // slt 3'b010: FullResult = SLT; // slt
3'b011: FullResult = SLTU; // sltu 3'b011: FullResult = SLTU; // sltu
3'b100: FullResult = A ^ B; // xor 3'b100: FullResult = A ^ B; // xor
3'b101: FullResult = Shift; // sra or srl
3'b110: FullResult = A | B; // or 3'b110: FullResult = A | B; // or
3'b111: FullResult = A & B; // and 3'b111: FullResult = A & B; // and
endcase endcase

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@ -27,20 +27,16 @@
module shifter ( module shifter (
input logic [`XLEN-1:0] a, input logic [`XLEN-1:0] a,
input logic [5:0] amt, input logic [`LOG_XLEN-1:0] amt,
input logic right, arith, w64, input logic right, arith, w64,
output logic [`XLEN-1:0] y); output logic [`XLEN-1:0] y);
localparam BITS = $clog2(`XLEN);
logic [2*`XLEN-2:0] z, zshift; logic [2*`XLEN-2:0] z, zshift;
logic [BITS-1:0] amttrunc, offset; logic [`LOG_XLEN-1:0] amttrunc, offset;
// The best shifter architecture differs based on `XLEN. // Handle left and right shifts with a funnel shifter.
// for RV32, only 32-bit shifts are needed. These are // For RV32, only 32-bit shifts are needed.
// most efficiently implemented with a funnel shifter. // For RV64, 32 and 64-bit shifts are needed, with sign extension.
// For RV64, 32 and 64-bit shifts are needed, with sign
// extension.
// funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
generate generate
@ -50,7 +46,7 @@ module shifter (
if (arith) z = {{31{a[31]}}, a}; if (arith) z = {{31{a[31]}}, a};
else z = {31'b0, a}; else z = {31'b0, a};
else z = {a, 31'b0}; else z = {a, 31'b0};
assign amttrunc = amt[4:0]; // shift amount assign amttrunc = amt; // shift amount
end else begin:shifter // RV64 end else begin:shifter // RV64
always_comb // funnel mux always_comb // funnel mux
if (w64) begin // 32-bit shifts if (w64) begin // 32-bit shifts
@ -64,7 +60,7 @@ module shifter (
else z = {63'b0, a}; else z = {63'b0, a};
else z = {a, 63'b0}; else z = {a, 63'b0};
end end
assign amttrunc = w64 ? {1'b0, amt[4:0]} : amt[5:0]; // 32 or 64-bit shift assign amttrunc = w64 ? {1'b0, amt[4:0]} : amt; // 32 or 64-bit shift
end end
endgenerate endgenerate