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Moved & ~StallM from FSM into DivStartE

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David Harris 2021-10-10 11:49:32 -07:00
parent 635fe181f8
commit 2759f1fcb1
1 changed files with 2 additions and 3 deletions
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wally-pipelined/src/muldiv/intdivrestoring.sv
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@ -54,7 +54,7 @@ module intdivrestoring (
////////////////////////////// //////////////////////////////
// Divider control signals // Divider control signals
assign DivStartE = DivE & ~BusyE & ~DivDoneM; assign DivStartE = DivE & ~BusyE & ~DivDoneM & ~StallM;
assign DivBusyE = BusyE | DivStartE; assign DivBusyE = BusyE | DivStartE;
// Handle sign extension for W-type instructions // Handle sign extension for W-type instructions
@ -88,7 +88,6 @@ module intdivrestoring (
////////////////////////////// //////////////////////////////
// registers before division steps // registers before division steps
// *** maybe change this stuff to M stage
flopen #(`XLEN) wreg(clk, DivBusyE, WNextE, WM[0]); flopen #(`XLEN) wreg(clk, DivBusyE, WNextE, WM[0]);
flopen #(`XLEN) xreg(clk, DivBusyE, XQNextE, XQM[0]); flopen #(`XLEN) xreg(clk, DivBusyE, XQNextE, XQM[0]);
flopen #(`XLEN) dabsreg(clk, DivStartE, DAbsBE, DAbsBM); flopen #(`XLEN) dabsreg(clk, DivStartE, DAbsBE, DAbsBM);
@ -118,7 +117,7 @@ module intdivrestoring (
always_ff @(posedge clk) always_ff @(posedge clk)
if (reset) begin if (reset) begin
BusyE = 0; DivDoneM = 0; step = 0; BusyE = 0; DivDoneM = 0; step = 0;
end else if (DivStartE & ~StallM) begin end else if (DivStartE) begin
if (Div0E) DivDoneM = 1; if (Div0E) DivDoneM = 1;
else begin else begin
BusyE = 1; step = 0; BusyE = 1; step = 0;