From 2759f1fcb14d3f87f12427c376abdd45f1b079a7 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 10 Oct 2021 11:49:32 -0700
Subject: [PATCH] Moved & ~StallM from FSM into DivStartE

---
 wally-pipelined/src/muldiv/intdivrestoring.sv | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/wally-pipelined/src/muldiv/intdivrestoring.sv b/wally-pipelined/src/muldiv/intdivrestoring.sv
index b403db47e..2d7d365f0 100644
--- a/wally-pipelined/src/muldiv/intdivrestoring.sv
+++ b/wally-pipelined/src/muldiv/intdivrestoring.sv
@@ -54,7 +54,7 @@ module intdivrestoring (
   //////////////////////////////
 
   // Divider control signals
-  assign DivStartE = DivE & ~BusyE & ~DivDoneM; 
+  assign DivStartE = DivE & ~BusyE & ~DivDoneM & ~StallM; 
   assign DivBusyE = BusyE | DivStartE;
 
   // Handle sign extension for W-type instructions
@@ -88,7 +88,6 @@ module intdivrestoring (
   //////////////////////////////
 
   // registers before division steps
-  // *** maybe change this stuff to M stage
   flopen #(`XLEN) wreg(clk, DivBusyE, WNextE, WM[0]); 
   flopen #(`XLEN) xreg(clk, DivBusyE, XQNextE, XQM[0]);
   flopen #(`XLEN) dabsreg(clk, DivStartE, DAbsBE, DAbsBM);
@@ -118,7 +117,7 @@ module intdivrestoring (
  always_ff @(posedge clk) 
     if (reset) begin
         BusyE = 0; DivDoneM = 0; step = 0; 
-    end else if (DivStartE & ~StallM) begin 
+    end else if (DivStartE) begin 
         if (Div0E) DivDoneM = 1;
         else begin
             BusyE = 1; step = 0;