diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv
index 3cf465268..8067ba412 100644
--- a/src/rvvi/packetizer.sv
+++ b/src/rvvi/packetizer.sv
@@ -34,13 +34,6 @@ module packetizer import cvw::*; #(parameter cvw_t P,
   input  logic m_axi_aclk, m_axi_aresetn,
   output logic RVVIStall,
   // axi 4 write address channel
-  output logic [3:0] 	   m_axi_awid,
-  output logic [12:0] 	   m_axi_awaddr,
-  output logic [7:0] 	   m_axi_awlen,
-  output logic [2:0] 	   m_axi_awsize,
-  output logic [1:0] 	   m_axi_awburst,
-  output logic [3:0] 	   m_axi_awcache,
-  output logic             m_axi_awvalid,
   input  logic  		   m_axi_awready,
   // axi 4 write data channel
   output logic [31:0]      m_axi_wdata,
@@ -122,13 +115,6 @@ module packetizer import cvw::*; #(parameter cvw_t P,
   assign BytesInFrame = 12'd76;
   assign BurstDone = WordCount == (BytesInFrame[11:2] - 1'b1);
 
-  assign m_axi_awid = '0;
-  assign m_axi_awaddr = '0; // *** bug update to be based on the correct address during each beat.
-  assign m_axi_awlen = BytesInFrame[11:2];
-  assign m_axi_awsize = 3'b010; // 4 bytes
-  assign m_axi_awburst = 2'b01; // increment
-  assign m_axi_awcache = '0;
-  assign m_axi_awvalid = (CurrState == STATE_RDY & valid) | CurrState == STATE_TRANS;
   genvar index;
   for (index = 0; index < TotalFrameLengthBytes/4; index++) begin 
     assign TotalFrameWords[index] = TotalFrame[(index*32)+32-1 : (index*32)];
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index ed511da68..2bcabbfa4 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -601,13 +601,6 @@ module testbench;
     // but I switched to using https://github.com/alexforencich/verilog-ethernet
     // so most arn't needed anymore.  *** remove once I've confirmed this
     // works in synthesis.
-    logic [3:0]                                       m_axi_awid;
-    logic [12:0]                                      m_axi_awaddr;
-    logic [7:0]                                       m_axi_awlen;
-    logic [2:0]                                       m_axi_awsize;
-    logic [1:0]                                       m_axi_awburst;
-    logic [3:0]                                       m_axi_awcache;
-    logic                                             m_axi_awvalid;
     logic                                             m_axi_awready;
     // axi 4 write data channel
     logic [31:0]                                      m_axi_wdata;
@@ -644,7 +637,6 @@ module testbench;
     logic                                             rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
 
     packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall,
-      .m_axi_awid, .m_axi_awaddr, .m_axi_awlen, .m_axi_awsize, .m_axi_awburst, .m_axi_awcache, .m_axi_awvalid,
       .m_axi_awready, .m_axi_wdata, .m_axi_wstrb, .m_axi_wlast, .m_axi_wvalid, .m_axi_wready, .m_axi_bid,
       .m_axi_bresp, .m_axi_bvalid, .m_axi_bready, .m_axi_arid, .m_axi_araddr, .m_axi_arlen, .m_axi_arsize,
       .m_axi_arburst, .m_axi_arcache, .m_axi_arvalid, .m_axi_arready, .m_axi_rid, .m_axi_rdata, .m_axi_rresp,