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ZK cleanup, check no LLEN > XLEN without D$, add half and quad float load/store to instruction name decoder

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This commit is contained in:
David Harris 2024-03-10 22:03:57 -07:00
parent 837abf1d9e
commit 2580d37fc0
8 changed files with 33 additions and 31 deletions
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7
src/ieu/bmu/bmuctrl.sv
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@ -126,7 +126,7 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulr
17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // ZBC instruction
endcase
if (P.ZBKC_SUPPORTED | P.ZBC_SUPPORTED) begin // ZBKC
if (P.ZBKC_SUPPORTED | P.ZBC_SUPPORTED) begin
casez({OpD, Funct7D, Funct3D})
17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // clmul
17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulh
@ -240,13 +240,10 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
endcase
end
if (P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) begin // ZKND and ZKNE shared instructions
if ((P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) & P.XLEN == 64) begin // ZKND and ZKNE shared instructions
casez({OpD, Funct7D, Funct3D})
17'b0010011_0011000_001: if (Rs2D[4] == 1'b1)
BMUControlsD = `BMUCTRLW'b000_0111_0011_1_0_0_1_0_0_0_0_0; // aes64ks1i - key schedule istr1 ... Don't know why this works here only ... P.XLEN is not 64 bits?
endcase
if (P.XLEN==64)
casez({OpD, Funct7D, Funct3D})
17'b0110011_0111111_000: BMUControlsD = `BMUCTRLW'b000_0111_0100_1_0_0_1_0_0_0_0_0; // aes64ks2 - key schedule istr2
endcase
end

6
testbench/common/instrNameDecTB.sv
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@ -341,10 +341,14 @@ module instrNameDecTB(
else if (funct7 == 7'b1011011 & funct3 == 3'b000) name = "FMVP.Q.X";
else if (funct7 == 7'b1100001 & funct3 == 3'b001 & rs2 == 5'b01000) name = "FCVTMOD.W.D";
else name = "ILLEGAL";
10'b0000111_001: name = "FLH";
10'b0000111_010: name = "FLW";
10'b0100111_010: name = "FSW";
10'b0000111_011: name = "FLD";
10'b0000111_100: name = "FLQ";
10'b0100111_001: name = "FSH";
10'b0100111_010: name = "FSW";
10'b0100111_011: name = "FSD";
10'b0100111_100: name = "FSQ";
default: name = "ILLEGAL";
endcase
endmodule

1
testbench/common/riscvassertions.sv
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@ -66,6 +66,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $fatal(1, "ZCF or ZCD requires ZCA");
assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F");
assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");
assert ((P.LLEN == P.XLEN) || (P.DCACHE_SUPPORTED)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
end
endmodule