diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv
index 63021864f..8193efbff 100644
--- a/src/ieu/bmu/bmuctrl.sv
+++ b/src/ieu/bmu/bmuctrl.sv
@@ -126,7 +126,7 @@ module bmuctrl import cvw::*;  #(parameter cvw_t P) (
         17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0;  // clmulr
         17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0;  // ZBC instruction
       endcase
-    if (P.ZBKC_SUPPORTED | P.ZBC_SUPPORTED) begin   // ZBKC
+    if (P.ZBKC_SUPPORTED | P.ZBC_SUPPORTED) begin   
       casez({OpD, Funct7D, Funct3D})
         17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0;  // clmul
         17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0;  // clmulh
@@ -165,10 +165,10 @@ module bmuctrl import cvw::*;  #(parameter cvw_t P) (
     
     if (P.ZBKB_SUPPORTED) begin // ZBKB Bitmanip
       casez({OpD,Funct7D, Funct3D})
-        17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_1_0_0_0_0_0; // pack
-        17'b0110011_0000100_111: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_1_0_0_0_0_0;  //packh
+        17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_1_0_0_0_0_0;  // pack
+        17'b0110011_0000100_111: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_1_0_0_0_0_0;  // packh
         17'b0010011_0110100_101: if (Rs2D == 5'b00111)
-                                 BMUControlsD = `BMUCTRLW'b000_0100_0000_1_1_0_1_0_0_0_0_0;  //brev8
+                                 BMUControlsD = `BMUCTRLW'b000_0100_0000_1_1_0_1_0_0_0_0_0;  // brev8
       endcase
       if (P.XLEN==32)
         casez({OpD, Funct7D, Funct3D})
@@ -240,15 +240,12 @@ module bmuctrl import cvw::*;  #(parameter cvw_t P) (
         endcase
     end  
     
-    if (P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) begin // ZKND and ZKNE shared instructions
+    if ((P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) & P.XLEN == 64) begin // ZKND and ZKNE shared instructions
       casez({OpD, Funct7D, Funct3D})
         17'b0010011_0011000_001: if (Rs2D[4] == 1'b1)
                                    BMUControlsD = `BMUCTRLW'b000_0111_0011_1_0_0_1_0_0_0_0_0;  // aes64ks1i - key schedule istr1 ... Don't know why this works here only ... P.XLEN is not 64 bits?
-      endcase
-      if (P.XLEN==64)
-        casez({OpD, Funct7D, Funct3D})
           17'b0110011_0111111_000: BMUControlsD = `BMUCTRLW'b000_0111_0100_1_0_0_1_0_0_0_0_0;  // aes64ks2 - key schedule istr2
-        endcase
+      endcase
     end
 
     if (P.ZKNH_SUPPORTED) begin // ZKNH
diff --git a/src/ieu/kmu/zipper.sv b/src/ieu/kmu/zipper.sv
index 131bdbdab..2cc0a3a18 100644
--- a/src/ieu/kmu/zipper.sv
+++ b/src/ieu/kmu/zipper.sv
@@ -35,10 +35,10 @@ module zipper #(parameter WIDTH=64) (
    genvar 		     i;
    
    for (i=0; i<WIDTH/2; i+=1) begin: loop
-      assign zip[2*i]         = A[i];
-      assign zip[2*i+1]       = A[i + WIDTH/2];      
-      assign unzip[i]         = A[2*i];
-      assign unzip[i+WIDTH/2] = A[2*i+1];
+      assign zip[2*i]           = A[i];
+      assign zip[2*i + 1]       = A[i + WIDTH/2];      
+      assign unzip[i]           = A[2*i];
+      assign unzip[i + WIDTH/2] = A[2*i + 1];
    end
    
    mux2 #(WIDTH) ZipMux(zip, unzip, ZipSelect, ZipResult);   
diff --git a/src/ieu/kmu/zknd32.sv b/src/ieu/kmu/zknd32.sv
index e6f1a5c16..e7542dc08 100644
--- a/src/ieu/kmu/zknd32.sv
+++ b/src/ieu/kmu/zknd32.sv
@@ -36,8 +36,8 @@ module zknd32 #(parameter WIDTH=32) (
    logic [31:0] 	     aes32dsiRes, aes32dsmiRes;
   
    // RV32
-   aes32dsi aes32dsi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32dsiRes));
-   aes32dsmi aes32dsmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32dsmiRes));
+   aes32dsi aes32dsi(.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32dsiRes));
+   aes32dsmi aes32dsmi(.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32dsmiRes));
    
-   mux2 #(WIDTH) zkndmux (aes32dsiRes, aes32dsmiRes, ZKNDSelect[0], ZKNDResult);
+   mux2 #(WIDTH) zkndmux(aes32dsiRes, aes32dsmiRes, ZKNDSelect[0], ZKNDResult);
 endmodule
diff --git a/src/ieu/kmu/zknd64.sv b/src/ieu/kmu/zknd64.sv
index 78ad47cb9..b1cf869e4 100644
--- a/src/ieu/kmu/zknd64.sv
+++ b/src/ieu/kmu/zknd64.sv
@@ -37,11 +37,11 @@ module zknd64 #(parameter WIDTH=32) (
    logic [63:0] 	     aes64dsRes, aes64dsmRes, aes64imRes, aes64ks1iRes, aes64ks2Res;
    
    // RV64
-   aes64ds aes64ds (.rs1(A), .rs2(B), .DataOut(aes64dsRes));
-   aes64dsm aes64dsm (.rs1(A), .rs2(B), .DataOut(aes64dsmRes));
-   aes64im aes64im (.rs1(A), .DataOut(aes64imRes));
-   aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
-   aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res));
+   aes64ds   aes64ds(.rs1(A), .rs2(B), .DataOut(aes64dsRes));
+   aes64dsm  aes64dsm(.rs1(A), .rs2(B), .DataOut(aes64dsmRes));
+   aes64im   aes64im(.rs1(A), .DataOut(aes64imRes));
+   aes64ks1i aes64ks1i(.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
+   aes64ks2  aes64ks2(.rs2(B), .rs1(A), .rd(aes64ks2Res));
    
-   mux5 #(WIDTH) zkndmux (aes64dsRes, aes64dsmRes, aes64imRes, aes64ks1iRes, aes64ks2Res, ZKNDSelect, ZKNDResult);
+   mux5 #(WIDTH) zkndmux(aes64dsRes, aes64dsmRes, aes64imRes, aes64ks1iRes, aes64ks2Res, ZKNDSelect, ZKNDResult);
 endmodule
diff --git a/src/ieu/kmu/zkne32.sv b/src/ieu/kmu/zkne32.sv
index a595d975e..8ca2b4413 100644
--- a/src/ieu/kmu/zkne32.sv
+++ b/src/ieu/kmu/zkne32.sv
@@ -35,8 +35,8 @@ module zkne32 #(parameter WIDTH=32) (
    logic [31:0] 	     aes32esiRes, aes32esmiRes;
    
    // RV32
-   aes32esi aes32esi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32esiRes));
-   aes32esmi aes32esmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32esmiRes));
+   aes32esi  aes32esi(.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32esiRes));
+   aes32esmi aes32esmi(.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32esmiRes));
    
-   mux2 #(WIDTH) zknemux (aes32esiRes, aes32esmiRes, ZKNESelect[0], ZKNEResult);
+   mux2 #(WIDTH) zknemux(aes32esiRes, aes32esmiRes, ZKNESelect[0], ZKNEResult);
 endmodule
diff --git a/src/ieu/kmu/zkne64.sv b/src/ieu/kmu/zkne64.sv
index fbba056a7..f71885355 100644
--- a/src/ieu/kmu/zkne64.sv
+++ b/src/ieu/kmu/zkne64.sv
@@ -37,11 +37,11 @@ module zkne64 #(parameter WIDTH=32) (
    logic [63:0] 	     aes64esRes, aes64esmRes, aes64ks1iRes, aes64ks2Res;
    
    // RV64
-   aes64es aes64es (.rs1(A), .rs2(B), .DataOut(aes64esRes));
-   aes64esm aes64esm (.rs1(A), .rs2(B), .DataOut(aes64esmRes));
-   aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
-   aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res));
+   aes64es   aes64es(.rs1(A), .rs2(B), .DataOut(aes64esRes));
+   aes64esm  aes64esm(.rs1(A), .rs2(B), .DataOut(aes64esmRes));
+   aes64ks1i aes64ks1i(.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
+   aes64ks2  aes64ks2(.rs2(B), .rs1(A), .rd(aes64ks2Res));
    
    // 010 is a placeholder to match the select of ZKND's AES64KS1I since they share some instruction
-   mux5 #(WIDTH) zknemux (aes64esRes, aes64esmRes, 64'b0, aes64ks1iRes, aes64ks2Res, ZKNESelect, ZKNEResult);   
+   mux5 #(WIDTH) zknemux(aes64esRes, aes64esmRes, 64'b0, aes64ks1iRes, aes64ks2Res, ZKNESelect, ZKNEResult);   
 endmodule
diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv
index 3c702ffd5..b433b2ed8 100644
--- a/testbench/common/instrNameDecTB.sv
+++ b/testbench/common/instrNameDecTB.sv
@@ -341,10 +341,14 @@ module instrNameDecTB(
                        else if (funct7 == 7'b1011011 & funct3 == 3'b000) name = "FMVP.Q.X";
                        else if (funct7 == 7'b1100001 & funct3 == 3'b001 & rs2 == 5'b01000) name = "FCVTMOD.W.D";
                        else                              name = "ILLEGAL";
+      10'b0000111_001: name = "FLH";
       10'b0000111_010: name = "FLW";
-      10'b0100111_010: name = "FSW";
       10'b0000111_011: name = "FLD";
+      10'b0000111_100: name = "FLQ";
+      10'b0100111_001: name = "FSH";
+      10'b0100111_010: name = "FSW";
       10'b0100111_011: name = "FSD";
+      10'b0100111_100: name = "FSQ";
       default:         name = "ILLEGAL";
     endcase
 endmodule
diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv
index b439b3d75..3f50d3f7c 100644
--- a/testbench/common/riscvassertions.sv
+++ b/testbench/common/riscvassertions.sv
@@ -66,6 +66,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
     assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $fatal(1, "ZCF or ZCD requires ZCA");
     assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F");
     assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");   
+    assert ((P.LLEN == P.XLEN) || (P.DCACHE_SUPPORTED)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
   end
 
 endmodule