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Rose Thompson 2024-02-23 14:11:18 -06:00
commit 252ca5b925
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config/derivlist.txt
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@ -2,7 +2,7 @@
## derivlist.txt ## derivlist.txt
## Wally Derivative Configuration List ## Wally Derivative Configuration List
## ##
## Written: David_Harris@hmc.edu ## Written: David_Harris@hmc.edu, kekim@hmc.edu
## Created: 29 January 2024 ## Created: 29 January 2024
## Modified: ## Modified:
## ##
@ -588,3 +588,490 @@ IEEE754 1
deriv fdqh_ieee_rv64gc fdqh_rv64gc deriv fdqh_ieee_rv64gc fdqh_rv64gc
IEEE754 1 IEEE754 1
#### MORE DIVIDER variants
#### F_only, RK variable
deriv f_div_2_1_rv32gc div_2_1_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv f_div_2_2_rv32gc div_2_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv f_div_2_4_rv32gc div_2_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv f_div_4_1_rv32gc div_4_1_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv f_div_4_2_rv32gc div_4_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv f_div_2_1_rv64gc div_2_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv f_div_2_2_rv64gc div_2_2_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv f_div_2_4_rv64gc div_2_4_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv f_div_4_1_rv64gc div_4_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv f_div_4_2_rv64gc div_4_2_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv f_div_4_4_rv64gc div_4_4_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
#### FH_only, RK variable
deriv fh_div_2_1_rv32gc div_2_1_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fh_div_2_2_rv32gc div_2_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fh_div_2_4_rv32gc div_2_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fh_div_4_1_rv32gc div_4_1_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fh_div_4_2_rv32gc div_4_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fh_div_2_1_rv64gc div_2_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fh_div_2_2_rv64gc div_2_2_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fh_div_2_4_rv64gc div_2_4_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fh_div_4_1_rv64gc div_4_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fh_div_4_2_rv64gc div_4_2_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fh_div_4_4_rv64gc div_4_4_rv64gc
MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
# FD only , rk variable
deriv fd_div_2_1_rv32gc div_2_1_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fd_div_2_2_rv32gc div_2_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fd_div_2_4_rv32gc div_2_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fd_div_4_1_rv32gc div_4_1_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fd_div_4_2_rv32gc div_4_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fd_div_2_1_rv64gc div_2_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fd_div_2_2_rv64gc div_2_2_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fd_div_2_4_rv64gc div_2_4_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fd_div_4_1_rv64gc div_4_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fd_div_4_2_rv64gc div_4_2_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fd_div_4_4_rv64gc div_4_4_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
# FDH only , rk variable
deriv fdh_div_2_1_rv32gc div_2_1_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdh_div_2_2_rv32gc div_2_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdh_div_2_4_rv32gc div_2_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdh_div_4_1_rv32gc div_4_1_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdh_div_4_2_rv32gc div_4_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdh_div_2_1_rv64gc div_2_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdh_div_2_2_rv64gc div_2_2_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdh_div_2_4_rv64gc div_2_4_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdh_div_4_1_rv64gc div_4_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdh_div_4_2_rv64gc div_4_2_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdh_div_4_4_rv64gc div_4_4_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
# FDQ only , rk variable
deriv fdq_div_2_1_rv32gc div_2_1_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdq_div_2_2_rv32gc div_2_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdq_div_2_4_rv32gc div_2_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdq_div_4_1_rv32gc div_4_1_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdq_div_4_2_rv32gc div_4_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdq_div_2_1_rv64gc div_2_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdq_div_2_2_rv64gc div_2_2_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdq_div_2_4_rv64gc div_2_4_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdq_div_4_1_rv64gc div_4_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdq_div_4_2_rv64gc div_4_2_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
deriv fdq_div_4_4_rv64gc div_4_4_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 0
# FDQH only , rk variable
deriv fdqh_div_2_1_rv32gc div_2_1_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdqh_div_2_2_rv32gc div_2_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdqh_div_2_4_rv32gc div_2_4_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdqh_div_4_1_rv32gc div_4_1_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdqh_div_4_2_rv32gc div_4_2_rv32gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdqh_div_2_1_rv64gc div_2_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdqh_div_2_2_rv64gc div_2_2_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdqh_div_2_4_rv64gc div_2_4_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdqh_div_4_1_rv64gc div_4_1_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdqh_div_4_2_rv64gc div_4_2_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
deriv fdqh_div_4_4_rv64gc div_4_4_rv64gc
MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
ZFH_SUPPORTED 1
#### DIVIDER VARIANTS WITH IEEE
deriv f_ieee_div_2_1_rv32gc f_div_2_1_rv32gc
IEEE754 1
deriv f_ieee_div_2_2_rv32gc f_div_2_2_rv32gc
IEEE754 1
deriv f_ieee_div_2_4_rv32gc f_div_2_4_rv32gc
IEEE754 1
deriv f_ieee_div_4_1_rv32gc f_div_4_1_rv32gc
IEEE754 1
deriv f_ieee_div_4_2_rv32gc f_div_4_2_rv32gc
IEEE754 1
deriv f_ieee_div_2_1_rv64gc f_div_2_1_rv64gc
IEEE754 1
deriv f_ieee_div_2_2_rv64gc f_div_2_2_rv64gc
IEEE754 1
deriv f_ieee_div_2_4_rv64gc f_div_2_4_rv64gc
IEEE754 1
deriv f_ieee_div_4_1_rv64gc f_div_4_1_rv64gc
IEEE754 1
deriv f_ieee_div_4_2_rv64gc f_div_4_2_rv64gc
IEEE754 1
deriv f_ieee_div_4_4_rv64gc f_div_4_4_rv64gc
IEEE754 1
#### FH_only, RK variable
deriv fh_ieee_div_2_1_rv32gc fh_div_2_1_rv32gc
IEEE754 1
deriv fh_ieee_div_2_2_rv32gc fh_div_2_2_rv32gc
IEEE754 1
deriv fh_ieee_div_2_4_rv32gc fh_div_2_4_rv32gc
IEEE754 1
deriv fh_ieee_div_4_1_rv32gc fh_div_4_1_rv32gc
IEEE754 1
deriv fh_ieee_div_4_2_rv32gc fh_div_4_2_rv32gc
IEEE754 1
deriv fh_ieee_div_2_1_rv64gc fh_div_2_1_rv64gc
IEEE754 1
deriv fh_ieee_div_2_2_rv64gc fh_div_2_2_rv64gc
IEEE754 1
deriv fh_ieee_div_2_4_rv64gc fh_div_2_4_rv64gc
IEEE754 1
deriv fh_ieee_div_4_1_rv64gc fh_div_4_1_rv64gc
IEEE754 1
deriv fh_ieee_div_4_2_rv64gc fh_div_4_2_rv64gc
IEEE754 1
deriv fh_ieee_div_4_4_rv64gc fh_div_4_4_rv64gc
IEEE754 1
# FD only , rk variable
deriv fd_ieee_div_2_1_rv32gc fd_div_2_1_rv32gc
IEEE754 1
deriv fd_ieee_div_2_2_rv32gc fd_div_2_2_rv32gc
IEEE754 1
deriv fd_ieee_div_2_4_rv32gc fd_div_2_4_rv32gc
IEEE754 1
deriv fd_ieee_div_4_1_rv32gc fd_div_4_1_rv32gc
IEEE754 1
deriv fd_ieee_div_4_2_rv32gc fd_div_4_2_rv32gc
IEEE754 1
deriv fd_ieee_div_2_1_rv64gc fd_div_2_1_rv64gc
IEEE754 1
deriv fd_ieee_div_2_2_rv64gc fd_div_2_2_rv64gc
IEEE754 1
deriv fd_ieee_div_2_4_rv64gc fd_div_2_4_rv64gc
IEEE754 1
deriv fd_ieee_div_4_1_rv64gc fd_div_4_1_rv64gc
IEEE754 1
deriv fd_ieee_div_4_2_rv64gc fd_div_4_2_rv64gc
IEEE754 1
deriv fd_ieee_div_4_4_rv64gc fd_div_4_4_rv64gc
IEEE754 1
# FDH only , rk variable
deriv fdh_ieee_div_2_1_rv32gc fdh_div_2_1_rv32gc
IEEE754 1
deriv fdh_ieee_div_2_2_rv32gc fdh_div_2_2_rv32gc
IEEE754 1
deriv fdh_ieee_div_2_4_rv32gc fdh_div_2_4_rv32gc
IEEE754 1
deriv fdh_ieee_div_4_1_rv32gc fdh_div_4_1_rv32gc
IEEE754 1
deriv fdh_ieee_div_4_2_rv32gc fdh_div_4_2_rv32gc
IEEE754 1
deriv fdh_ieee_div_2_1_rv64gc fdh_div_2_1_rv64gc
IEEE754 1
deriv fdh_ieee_div_2_2_rv64gc fdh_div_2_2_rv64gc
IEEE754 1
deriv fdh_ieee_div_2_4_rv64gc fdh_div_2_4_rv64gc
IEEE754 1
deriv fdh_ieee_div_4_1_rv64gc fdh_div_4_1_rv64gc
IEEE754 1
deriv fdh_ieee_div_4_2_rv64gc fdh_div_4_2_rv64gc
IEEE754 1
deriv fdh_ieee_div_4_4_rv64gc fdh_div_4_4_rv64gc
IEEE754 1
# FDQ only , rk variable
deriv fdq_ieee_div_2_1_rv32gc fdq_div_2_1_rv32gc
IEEE754 1
deriv fdq_ieee_div_2_2_rv32gc fdq_div_2_2_rv32gc
IEEE754 1
deriv fdq_ieee_div_2_4_rv32gc fdq_div_2_4_rv32gc
IEEE754 1
deriv fdq_ieee_div_4_1_rv32gc fdq_div_4_1_rv32gc
IEEE754 1
deriv fdq_ieee_div_4_2_rv32gc fdq_div_4_2_rv32gc
IEEE754 1
deriv fdq_ieee_div_2_1_rv64gc fdq_div_2_1_rv64gc
IEEE754 1
deriv fdq_ieee_div_2_2_rv64gc fdq_div_2_2_rv64gc
IEEE754 1
deriv fdq_ieee_div_2_4_rv64gc fdq_div_2_4_rv64gc
IEEE754 1
deriv fdq_ieee_div_4_1_rv64gc fdq_div_4_1_rv64gc
IEEE754 1
deriv fdq_ieee_div_4_2_rv64gc fdq_div_4_2_rv64gc
IEEE754 1
deriv fdq_ieee_div_4_4_rv64gc fdq_div_4_4_rv64gc
IEEE754 1
# FDQH only , rk variable
deriv fdqh_ieee_div_2_1_rv32gc fdqh_div_2_1_rv32gc
IEEE754 1
deriv fdqh_ieee_div_2_2_rv32gc fdqh_div_2_2_rv32gc
IEEE754 1
deriv fdqh_ieee_div_2_4_rv32gc fdqh_div_2_4_rv32gc
IEEE754 1
deriv fdqh_ieee_div_4_1_rv32gc fdqh_div_4_1_rv32gc
IEEE754 1
deriv fdqh_ieee_div_4_2_rv32gc fdqh_div_4_2_rv32gc
IEEE754 1
deriv fdqh_ieee_div_2_1_rv64gc fdqh_div_2_1_rv64gc
IEEE754 1
deriv fdqh_ieee_div_2_2_rv64gc fdqh_div_2_2_rv64gc
IEEE754 1
deriv fdqh_ieee_div_2_4_rv64gc fdqh_div_2_4_rv64gc
IEEE754 1
deriv fdqh_ieee_div_4_1_rv64gc fdqh_div_4_1_rv64gc
IEEE754 1
deriv fdqh_ieee_div_4_2_rv64gc fdqh_div_4_2_rv64gc
IEEE754 1
deriv fdqh_ieee_div_4_4_rv64gc fdqh_div_4_4_rv64gc
IEEE754 1

105
sim/regression-wally
View File

@ -33,6 +33,7 @@ os.chdir(regressionDir)
coverage = '-coverage' in sys.argv coverage = '-coverage' in sys.argv
fp = '-fp' in sys.argv fp = '-fp' in sys.argv
nightly = '-nightly' in sys.argv nightly = '-nightly' in sys.argv
softfloat = '-softfloat' in sys.argv
TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
# name: the name of this test configuration (used in printing human-readable # name: the name of this test configuration (used in printing human-readable
@ -267,18 +268,17 @@ if (nightly):
["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
# enable floating-point tests when lint is fixed # enable floating-point tests when lint is fixed
# ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]], ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
# ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]], ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],
# ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
# ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
# ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
# ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]], ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]],
# ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed
# ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
# ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
# ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
] ]
@ -310,6 +310,87 @@ for test in tests32e:
configs.append(tc) configs.append(tc)
# softfloat tests
if (softfloat):
configs = []
softfloatconfigs = ['fdh_ieee_rv32gc', 'fdqh_ieee_rv32gc', 'fdq_ieee_rv32gc', \
'fh_ieee_v32gc', 'f_ieee_rv64gc', 'fdqh_ieee_rv64gc', \
'fdq_ieee_rv64gc', 'div_2_1_rv32gc', 'div_2_2_rv32gc', \
'div_2_4_rv32gc', 'div_4_1_rv32gc', 'div_4_2_rv32gc', \
'div_4_4_rv32gc', 'fd_ieee_rv32gc', 'fh_ieee_rv32gc', \
'div_2_1_rv64gc', 'div_2_2_rv64gc', 'div_2_4_rv64gc', \
'div_4_1_rv64gc', 'div_4_2_rv64gc', 'div_4_4_rv64gc', \
'fd_ieee_rv64gc', 'fh_ieee_rv64gc', 'f_ieee_rv32gc']
softfloatconfigs = ['fdh_ieee_div_2_1_rv32gc', 'fdh_ieee_div_2_1_rv64gc', \
'fdh_ieee_div_2_2_rv32gc', 'fdh_ieee_div_2_2_rv64gc', 'fdh_ieee_div_2_4_rv32gc', \
'fdh_ieee_div_2_4_rv64gc', 'fdh_ieee_div_4_1_rv32gc', 'fdh_ieee_div_4_1_rv64gc', \
'fdh_ieee_div_4_2_rv32gc', 'fdh_ieee_div_4_2_rv64gc', 'fdh_ieee_div_4_4_rv64gc', \
'fdh_ieee_rv32gc', 'fd_ieee_div_2_1_rv32gc', 'fd_ieee_div_2_1_rv64gc', \
'fd_ieee_div_2_2_rv32gc', 'fd_ieee_div_2_2_rv64gc', 'fd_ieee_div_2_4_rv32gc', \
'fd_ieee_div_2_4_rv64gc', 'fd_ieee_div_4_1_rv32gc', 'fd_ieee_div_4_1_rv64gc', \
'fd_ieee_div_4_2_rv32gc', 'fd_ieee_div_4_2_rv64gc', 'fd_ieee_div_4_4_rv64gc', \
'fd_ieee_rv32gc', 'fd_ieee_rv64gc', 'fdqh_ieee_div_2_1_rv32gc', \
'fdqh_ieee_div_2_1_rv64gc', 'fdqh_ieee_div_2_2_rv32gc', 'fdqh_ieee_div_2_2_rv64gc', \
'fdqh_ieee_div_2_4_rv32gc', 'fdqh_ieee_div_2_4_rv64gc', 'fdqh_ieee_div_4_1_rv32gc', \
'fdqh_ieee_div_4_1_rv64gc', 'fdqh_ieee_div_4_2_rv32gc', 'fdqh_ieee_div_4_2_rv64gc',\
'fdqh_ieee_div_4_4_rv64gc', 'fdqh_ieee_rv32gc', 'fdqh_ieee_rv64gc', \
'fdq_ieee_div_2_1_rv32gc', 'fdq_ieee_div_2_1_rv64gc', 'fdq_ieee_div_2_2_rv32gc',\
'fdq_ieee_div_2_2_rv64gc', 'fdq_ieee_div_2_4_rv32gc', 'fdq_ieee_div_2_4_rv64gc', \
'fdq_ieee_div_4_1_rv32gc', 'fdq_ieee_div_4_1_rv64gc', 'fdq_ieee_div_4_2_rv32gc', \
'fdq_ieee_div_4_2_rv64gc', 'fdq_ieee_div_4_4_rv64gc', 'fdq_ieee_rv32gc', \
'fdq_ieee_rv64gc', 'fh_ieee_div_2_1_rv32gc', 'fh_ieee_div_2_1_rv64gc', \
'fh_ieee_div_2_2_rv32gc', 'fh_ieee_div_2_2_rv64gc', 'fh_ieee_div_2_4_rv32gc',\
'fh_ieee_div_2_4_rv64gc', 'fh_ieee_div_4_1_rv32gc', 'fh_ieee_div_4_1_rv64gc',\
'fh_ieee_div_4_2_rv32gc', 'fh_ieee_div_4_2_rv64gc', 'fh_ieee_div_4_4_rv64gc', \
'fh_ieee_rv32gc', 'fh_ieee_rv64gc', 'fh_ieee_v32gc', 'f_ieee_div_2_1_rv32gc', \
'f_ieee_div_2_1_rv64gc', 'f_ieee_div_2_2_rv32gc', 'f_ieee_div_2_2_rv64gc', \
'f_ieee_div_2_4_rv32gc', 'f_ieee_div_2_4_rv64gc', 'f_ieee_div_4_1_rv32gc', \
'f_ieee_div_4_1_rv64gc', 'f_ieee_div_4_2_rv32gc', 'f_ieee_div_4_2_rv64gc', \
'f_ieee_div_4_4_rv64gc', 'f_ieee_rv32gc', 'f_ieee_rv64gc']
for config in softfloatconfigs:
# div test case
divtest = TestCase(
name="div",
variant=config,
cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " div \n!",
grepstr="All Tests completed with 0 errors"
)
configs.insert(0,divtest)
# sqrt test case
sqrttest = TestCase(
name="sqrt",
variant=config,
cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " sqrt \n!",
grepstr="All Tests completed with 0 errors"
)
#configs.append(sqrttest)
configs.insert(0,sqrttest)
# skip if divider variant config
if ("ieee" in config):
# cvtint test case
cvtinttest = TestCase(
name="cvtint",
variant=config,
cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " cvtint \n!",
grepstr="All Tests completed with 0 errors"
)
configs.append(cvtinttest)
# cvtfp test case
# WILL fail on F_only (refer to spec)
cvtfptest = TestCase(
name="cvtfp",
variant=config,
cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " cvtfp \n!",
grepstr="All Tests completed with 0 errors"
)
configs.append(cvtfptest)
import os import os
from multiprocessing import Pool, TimeoutError from multiprocessing import Pool, TimeoutError
@ -368,6 +449,8 @@ def main():
elif '-nightly' in sys.argv: elif '-nightly' in sys.argv:
TIMEOUT_DUR = 60*1440 # 1 day TIMEOUT_DUR = 60*1440 # 1 day
configs.append(getBuildrootTC(boot=False)) configs.append(getBuildrootTC(boot=False))
elif '-softfloat' in sys.argv:
TIMEOUT_DUR = 60*60 # seconds
else: else:
TIMEOUT_DUR = 10*60 # seconds TIMEOUT_DUR = 10*60 # seconds
configs.append(getBuildrootTC(boot=False)) configs.append(getBuildrootTC(boot=False))

55
sim/testfloat-batch.do Normal file
View File

@ -0,0 +1,55 @@
# testfloat-batch.do
#
# Modification by Oklahoma State University & Harvey Mudd College
# Use with Testbench
# James Stine, 2008; David Harris 2021; Kevin Kim 2024
# Go Cowboys!!!!!!
#
# Takes 1:10 to run RV64IC tests using gui
# run with vsim -do "do wally.do rv64ic riscvarchtest-64m"
onbreak {resume}
# create library
if [file exists wkdir/work_${1}_${2}] {
vdel -lib wkdir/work_${1}_${2} -all
}
vlib wkdir/work_${1}_${2}
# c# compile source files
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
# $num = the added words after the call
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697,7033
# Set WAV variable to avoid having any output to wave (to limit disk space)
quietly set WAV 0;
# Determine if nowave argument is provided this removes any output to
# a wlf or wave window to reduce disk space.
if {$WAV eq 0} {
puts "No wave output is selected"
} else {
puts "wave output is selected"
view wave
add log -recursive /*
do wave-fpu.do
}
# Change TEST_SIZE to only test certain FP width
# values are QP, DP, SP, HP or all for all tests
vopt +acc wkdir/work_${1}_${2}.testbenchfp -work wkdir/work_${1}_${2} -G TEST=$2 -G TEST_SIZE="all" -o testbenchopt
vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
#-- Run the Simulation
run -all

2
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output
View File

@ -1,3 +1,3 @@
0000000b # Test *** Number: Ecall from going from M mode to S mode 0000000b # Test *** Number: Ecall from going from M mode to S mode
00000002 # illegal instruction from truining on virtual memory with invalid satp address 00000001 # Instruction access fault (was illegal instruction) from turning on virtual memory with invalid satp address
00000009 # ecall from ending tests in S mode. 00000009 # ecall from ending tests in S mode.

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output
View File

@ -1,6 +1,6 @@
0000000b # Test *** Number: Ecall from going from M mode to S mode 0000000b # Test *** Number: Ecall from going from M mode to S mode
00000000 00000000
00000002 # illegal instruction from truining on virtual memory with invalid satp address 00000001 # Instruction access fault from turning on virtual memory with invalid satp address
00000000 00000000
00000009 # ecall from ending tests in S mode. 00000009 # ecall from ending tests in S mode.
00000000 00000000