From 824bc0dab74e59d4306b55b3d7bbd750119a9109 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 16 Feb 2024 11:12:57 -0800 Subject: [PATCH 01/10] Fixed expected value on WALLY-satp-invalid --- .../privilege/references/WALLY-satp-invalid-01.reference_output | 2 +- .../privilege/references/WALLY-satp-invalid-01.reference_output | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output index f0468cead..53a480fec 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-satp-invalid-01.reference_output @@ -1,3 +1,3 @@ 0000000b # Test *** Number: Ecall from going from M mode to S mode -00000002 # illegal instruction from truining on virtual memory with invalid satp address +00000001 # Instruction access fault (was illegal instruction) from turning on virtual memory with invalid satp address 00000009 # ecall from ending tests in S mode. \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output index e6728f2e0..8ad794f1d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output @@ -1,6 +1,6 @@ 0000000b # Test *** Number: Ecall from going from M mode to S mode 00000000 -00000002 # illegal instruction from truining on virtual memory with invalid satp address +00000001 # Instruction access fault from turning on virtual memory with invalid satp address 00000000 00000009 # ecall from ending tests in S mode. 00000000 \ No newline at end of file From ccf8d125b7d317cc369dfc1b9748b182f9871b13 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 19 Feb 2024 09:01:44 -0800 Subject: [PATCH 02/10] added updated dervlist --- config/derivlist.txt | 511 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 499 insertions(+), 12 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index c0cae3bd3..c1376e2a0 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -327,23 +327,23 @@ INSTR_CLASS_PRED 0 deriv bpred_GSHARE_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_1_rv32gc INSTR_CLASS_PRED 0 -deriv bpred_TWOBIT_6_16_10_0_rv32gc bpred_TWOBIT_6_16_10_1_rv32gc -INSTR_CLASS_PRED 0 +deriv bpred_TWOBIT_6_16_10_0_rv32gc bpred_GSHARE_6_16_10_0_rv32gc +BPRED_TYPE `BP_TWOBIT -deriv bpred_TWOBIT_8_16_10_0_rv32gc bpred_TWOBIT_8_16_10_1_rv32gc -INSTR_CLASS_PRED 0 +deriv bpred_TWOBIT_8_16_10_0_rv32gc bpred_GSHARE_8_16_10_0_rv32gc +BPRED_TYPE `BP_TWOBIT -deriv bpred_TWOBIT_10_16_10_0_rv32gc bpred_TWOBIT_10_16_10_1_rv32gc -INSTR_CLASS_PRED 0 +deriv bpred_TWOBIT_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_0_rv32gc +BPRED_TYPE `BP_TWOBIT -deriv bpred_TWOBIT_12_16_10_0_rv32gc bpred_TWOBIT_12_16_10_1_rv32gc -INSTR_CLASS_PRED 0 +deriv bpred_TWOBIT_12_16_10_0_rv32gc bpred_GSHARE_12_16_10_0_rv32gc +BPRED_TYPE `BP_TWOBIT -deriv bpred_TWOBIT_14_16_10_0_rv32gc bpred_TWOBIT_14_16_10_1_rv32gc -INSTR_CLASS_PRED 0 +deriv bpred_TWOBIT_14_16_10_0_rv32gc bpred_GSHARE_14_16_10_0_rv32gc +BPRED_TYPE `BP_TWOBIT -deriv bpred_TWOBIT_16_16_10_0_rv32gc bpred_TWOBIT_16_16_10_1_rv32gc -INSTR_CLASS_PRED 0 +deriv bpred_TWOBIT_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_0_rv32gc +BPRED_TYPE `BP_TWOBIT deriv bpred_GSHARE_10_2_10_0_rv32gc bpred_GSHARE_10_2_10_1_rv32gc INSTR_CLASS_PRED 0 @@ -588,3 +588,490 @@ IEEE754 1 deriv fdqh_ieee_rv64gc fdqh_rv64gc IEEE754 1 + +#### MORE DIVIDER variants + +#### F_only, RK variable +deriv f_div_2_1_rv32gc div_2_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_2_2_rv32gc div_2_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_2_4_rv32gc div_2_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_4_1_rv32gc div_4_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_4_2_rv32gc div_4_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_2_1_rv64gc div_2_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_2_2_rv64gc div_2_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_2_4_rv64gc div_2_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_4_1_rv64gc div_4_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_4_2_rv64gc div_4_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv f_div_4_4_rv64gc div_4_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + + +#### FH_only, RK variable +deriv fh_div_2_1_rv32gc div_2_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_2_2_rv32gc div_2_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_2_4_rv32gc div_2_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_4_1_rv32gc div_4_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_4_2_rv32gc div_4_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_2_1_rv64gc div_2_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_2_2_rv64gc div_2_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_2_4_rv64gc div_2_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_4_1_rv64gc div_4_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_4_2_rv64gc div_4_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fh_div_4_4_rv64gc div_4_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +# FD only , rk variable + +deriv fd_div_2_1_rv32gc div_2_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_2_2_rv32gc div_2_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_2_4_rv32gc div_2_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_4_1_rv32gc div_4_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_4_2_rv32gc div_4_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_2_1_rv64gc div_2_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_2_2_rv64gc div_2_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_2_4_rv64gc div_2_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_4_1_rv64gc div_4_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_4_2_rv64gc div_4_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fd_div_4_4_rv64gc div_4_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + + +# FDH only , rk variable + +deriv fdh_div_2_1_rv32gc div_2_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_2_2_rv32gc div_2_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_2_4_rv32gc div_2_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_4_1_rv32gc div_4_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_4_2_rv32gc div_4_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_2_1_rv64gc div_2_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_2_2_rv64gc div_2_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_2_4_rv64gc div_2_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_4_1_rv64gc div_4_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_4_2_rv64gc div_4_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdh_div_4_4_rv64gc div_4_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +# FDQ only , rk variable + +deriv fdq_div_2_1_rv32gc div_2_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_2_2_rv32gc div_2_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_2_4_rv32gc div_2_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_4_1_rv32gc div_4_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_4_2_rv32gc div_4_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_2_1_rv64gc div_2_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_2_2_rv64gc div_2_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_2_4_rv64gc div_2_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_4_1_rv64gc div_4_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_4_2_rv64gc div_4_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +deriv fdq_div_4_4_rv64gc div_4_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 0 + +# FDQH only , rk variable + +deriv fdqh_div_2_1_rv32gc div_2_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_2_2_rv32gc div_2_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_2_4_rv32gc div_2_4_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_4_1_rv32gc div_4_1_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_4_2_rv32gc div_4_2_rv32gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_2_1_rv64gc div_2_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_2_2_rv64gc div_2_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_2_4_rv64gc div_2_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_4_1_rv64gc div_4_1_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_4_2_rv64gc div_4_2_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +deriv fdqh_div_4_4_rv64gc div_4_4_rv64gc +MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0) +ZFH_SUPPORTED 1 + +#### DIVIDER VARIANTS WITH IEEE + +deriv f_ieee_div_2_1_rv32gc f_div_2_1_rv32gc +IEEE754 1 + +deriv f_ieee_div_2_2_rv32gc f_div_2_2_rv32gc +IEEE754 1 + +deriv f_ieee_div_2_4_rv32gc f_div_2_4_rv32gc +IEEE754 1 + +deriv f_ieee_div_4_1_rv32gc f_div_4_1_rv32gc +IEEE754 1 + +deriv f_ieee_div_4_2_rv32gc f_div_4_2_rv32gc +IEEE754 1 + +deriv f_ieee_div_2_1_rv64gc f_div_2_1_rv64gc +IEEE754 1 + +deriv f_ieee_div_2_2_rv64gc f_div_2_2_rv64gc +IEEE754 1 + +deriv f_ieee_div_2_4_rv64gc f_div_2_4_rv64gc +IEEE754 1 + +deriv f_ieee_div_4_1_rv64gc f_div_4_1_rv64gc +IEEE754 1 + +deriv f_ieee_div_4_2_rv64gc f_div_4_2_rv64gc +IEEE754 1 + +deriv f_ieee_div_4_4_rv64gc f_div_4_4_rv64gc +IEEE754 1 + +#### FH_only, RK variable +deriv fh_ieee_div_2_1_rv32gc fh_div_2_1_rv32gc +IEEE754 1 + +deriv fh_ieee_div_2_2_rv32gc fh_div_2_2_rv32gc +IEEE754 1 + +deriv fh_ieee_div_2_4_rv32gc fh_div_2_4_rv32gc +IEEE754 1 + +deriv fh_ieee_div_4_1_rv32gc fh_div_4_1_rv32gc +IEEE754 1 + +deriv fh_ieee_div_4_2_rv32gc fh_div_4_2_rv32gc +IEEE754 1 + +deriv fh_ieee_div_2_1_rv64gc fh_div_2_1_rv64gc +IEEE754 1 + +deriv fh_ieee_div_2_2_rv64gc fh_div_2_2_rv64gc +IEEE754 1 + +deriv fh_ieee_div_2_4_rv64gc fh_div_2_4_rv64gc +IEEE754 1 + +deriv fh_ieee_div_4_1_rv64gc fh_div_4_1_rv64gc +IEEE754 1 + +deriv fh_ieee_div_4_2_rv64gc fh_div_4_2_rv64gc +IEEE754 1 + +deriv fh_ieee_div_4_4_rv64gc fh_div_4_4_rv64gc +IEEE754 1 +# FD only , rk variable + +deriv fd_ieee_div_2_1_rv32gc fd_div_2_1_rv32gc +IEEE754 1 + +deriv fd_ieee_div_2_2_rv32gc fd_div_2_2_rv32gc +IEEE754 1 + +deriv fd_ieee_div_2_4_rv32gc fd_div_2_4_rv32gc +IEEE754 1 + +deriv fd_ieee_div_4_1_rv32gc fd_div_4_1_rv32gc +IEEE754 1 + +deriv fd_ieee_div_4_2_rv32gc fd_div_4_2_rv32gc +IEEE754 1 + +deriv fd_ieee_div_2_1_rv64gc fd_div_2_1_rv64gc +IEEE754 1 + +deriv fd_ieee_div_2_2_rv64gc fd_div_2_2_rv64gc +IEEE754 1 + +deriv fd_ieee_div_2_4_rv64gc fd_div_2_4_rv64gc +IEEE754 1 + +deriv fd_ieee_div_4_1_rv64gc fd_div_4_1_rv64gc +IEEE754 1 + +deriv fd_ieee_div_4_2_rv64gc fd_div_4_2_rv64gc +IEEE754 1 + +deriv fd_ieee_div_4_4_rv64gc fd_div_4_4_rv64gc +IEEE754 1 + +# FDH only , rk variable + +deriv fdh_ieee_div_2_1_rv32gc fdh_div_2_1_rv32gc +IEEE754 1 + +deriv fdh_ieee_div_2_2_rv32gc fdh_div_2_2_rv32gc +IEEE754 1 + +deriv fdh_ieee_div_2_4_rv32gc fdh_div_2_4_rv32gc +IEEE754 1 + +deriv fdh_ieee_div_4_1_rv32gc fdh_div_4_1_rv32gc +IEEE754 1 + +deriv fdh_ieee_div_4_2_rv32gc fdh_div_4_2_rv32gc +IEEE754 1 + +deriv fdh_ieee_div_2_1_rv64gc fdh_div_2_1_rv64gc +IEEE754 1 + +deriv fdh_ieee_div_2_2_rv64gc fdh_div_2_2_rv64gc +IEEE754 1 + +deriv fdh_ieee_div_2_4_rv64gc fdh_div_2_4_rv64gc +IEEE754 1 + +deriv fdh_ieee_div_4_1_rv64gc fdh_div_4_1_rv64gc +IEEE754 1 + +deriv fdh_ieee_div_4_2_rv64gc fdh_div_4_2_rv64gc +IEEE754 1 + +deriv fdh_ieee_div_4_4_rv64gc fdh_div_4_4_rv64gc +IEEE754 1 +# FDQ only , rk variable + +deriv fdq_ieee_div_2_1_rv32gc fdq_div_2_1_rv32gc +IEEE754 1 + +deriv fdq_ieee_div_2_2_rv32gc fdq_div_2_2_rv32gc +IEEE754 1 + +deriv fdq_ieee_div_2_4_rv32gc fdq_div_2_4_rv32gc +IEEE754 1 + +deriv fdq_ieee_div_4_1_rv32gc fdq_div_4_1_rv32gc +IEEE754 1 + +deriv fdq_ieee_div_4_2_rv32gc fdq_div_4_2_rv32gc +IEEE754 1 + +deriv fdq_ieee_div_2_1_rv64gc fdq_div_2_1_rv64gc +IEEE754 1 + +deriv fdq_ieee_div_2_2_rv64gc fdq_div_2_2_rv64gc +IEEE754 1 + +deriv fdq_ieee_div_2_4_rv64gc fdq_div_2_4_rv64gc +IEEE754 1 + +deriv fdq_ieee_div_4_1_rv64gc fdq_div_4_1_rv64gc +IEEE754 1 + +deriv fdq_ieee_div_4_2_rv64gc fdq_div_4_2_rv64gc +IEEE754 1 + +deriv fdq_ieee_div_4_4_rv64gc fdq_div_4_4_rv64gc +IEEE754 1 + +# FDQH only , rk variable + +deriv fdqh_ieee_div_2_1_rv32gc fdqh_div_2_1_rv32gc +IEEE754 1 + +deriv fdqh_ieee_div_2_2_rv32gc fdqh_div_2_2_rv32gc +IEEE754 1 + +deriv fdqh_ieee_div_2_4_rv32gc fdqh_div_2_4_rv32gc +IEEE754 1 + +deriv fdqh_ieee_div_4_1_rv32gc fdqh_div_4_1_rv32gc +IEEE754 1 + +deriv fdqh_ieee_div_4_2_rv32gc fdqh_div_4_2_rv32gc +IEEE754 1 + +deriv fdqh_ieee_div_2_1_rv64gc fdqh_div_2_1_rv64gc +IEEE754 1 + +deriv fdqh_ieee_div_2_2_rv64gc fdqh_div_2_2_rv64gc +IEEE754 1 + +deriv fdqh_ieee_div_2_4_rv64gc fdqh_div_2_4_rv64gc +IEEE754 1 + +deriv fdqh_ieee_div_4_1_rv64gc fdqh_div_4_1_rv64gc +IEEE754 1 + +deriv fdqh_ieee_div_4_2_rv64gc fdqh_div_4_2_rv64gc +IEEE754 1 + +deriv fdqh_ieee_div_4_4_rv64gc fdqh_div_4_4_rv64gc +IEEE754 1 + + From 354e1ca5c610b84d68adcaac8d82f805ff0e39a3 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 19 Feb 2024 09:06:35 -0800 Subject: [PATCH 03/10] lints --- config/derivlist.txt | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index c1376e2a0..279fbd3c5 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -2,7 +2,7 @@ ## derivlist.txt ## Wally Derivative Configuration List ## -## Written: David_Harris@hmc.edu +## Written: David_Harris@hmc.edu, kekim@hmc.edu ## Created: 29 January 2024 ## Modified: ## @@ -327,23 +327,23 @@ INSTR_CLASS_PRED 0 deriv bpred_GSHARE_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_1_rv32gc INSTR_CLASS_PRED 0 -deriv bpred_TWOBIT_6_16_10_0_rv32gc bpred_GSHARE_6_16_10_0_rv32gc -BPRED_TYPE `BP_TWOBIT +deriv bpred_TWOBIT_6_16_10_0_rv32gc bpred_TWOBIT_6_16_10_1_rv32gc +INSTR_CLASS_PRED 0 -deriv bpred_TWOBIT_8_16_10_0_rv32gc bpred_GSHARE_8_16_10_0_rv32gc -BPRED_TYPE `BP_TWOBIT +deriv bpred_TWOBIT_8_16_10_0_rv32gc bpred_TWOBIT_8_16_10_1_rv32gc +INSTR_CLASS_PRED 0 -deriv bpred_TWOBIT_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_0_rv32gc -BPRED_TYPE `BP_TWOBIT +deriv bpred_TWOBIT_10_16_10_0_rv32gc bpred_TWOBIT_10_16_10_1_rv32gc +INSTR_CLASS_PRED 0 -deriv bpred_TWOBIT_12_16_10_0_rv32gc bpred_GSHARE_12_16_10_0_rv32gc -BPRED_TYPE `BP_TWOBIT +deriv bpred_TWOBIT_12_16_10_0_rv32gc bpred_TWOBIT_12_16_10_1_rv32gc +INSTR_CLASS_PRED 0 -deriv bpred_TWOBIT_14_16_10_0_rv32gc bpred_GSHARE_14_16_10_0_rv32gc -BPRED_TYPE `BP_TWOBIT +deriv bpred_TWOBIT_14_16_10_0_rv32gc bpred_TWOBIT_14_16_10_1_rv32gc +INSTR_CLASS_PRED 0 -deriv bpred_TWOBIT_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_0_rv32gc -BPRED_TYPE `BP_TWOBIT +deriv bpred_TWOBIT_16_16_10_0_rv32gc bpred_TWOBIT_16_16_10_1_rv32gc +INSTR_CLASS_PRED 0 deriv bpred_GSHARE_10_2_10_0_rv32gc bpred_GSHARE_10_2_10_1_rv32gc INSTR_CLASS_PRED 0 From b815f17560004993f80cd529047ed9a4cddc05a4 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 20 Feb 2024 17:16:29 -0800 Subject: [PATCH 04/10] regression-wally handles softfloat --- sim/regression-wally | 114 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 104 insertions(+), 10 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index d06ac0b28..61f133fa9 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -33,6 +33,7 @@ os.chdir(regressionDir) coverage = '-coverage' in sys.argv fp = '-fp' in sys.argv nightly = '-nightly' in sys.argv +softfloat = '-softfloat' in sys.argv TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) # name: the name of this test configuration (used in printing human-readable @@ -161,6 +162,45 @@ for test in tests64gc: # run derivative configurations if requested if (nightly): + derivconfigtests = [ + ["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], + ["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + ["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], + + + ["f_rv32gc", ["arch32f", "arch32f_divsqrt"]], + ["fh_rv32gc", ["arch32f", "arch32f_divsqrt"]], + ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32d", "arch32d_divsqrt"]], + ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32d", "arch32d_divsqrt" ]], + ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32d", "arch32d_divsqrt"]], + ["f_rv64gc", ["arch64f", "arch64f_divsqrt"]], + ["fh_rv64gc", ["arch64f", "arch64f_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed + ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]], + ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]], + ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]], + ] + """ derivconfigtests = [ ["tlb2_rv32gc", ["wally32priv"]], ["tlb16_rv32gc", ["wally32priv"]], @@ -269,16 +309,16 @@ if (nightly): # enable floating-point tests when lint is fixed -# ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]], -# ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]], -# ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], -# ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], -# ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], -# ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]], -# ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed -# ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], -# ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], -# ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], + ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]], + ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]], + ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], + ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], + ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]], + ["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]], + ["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed + ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], + ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], + ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]], ] @@ -309,6 +349,58 @@ for test in tests32e: grepstr="All tests ran without failures") configs.append(tc) + +# softfloat tests +if (softfloat): + configs = [] + softfloatconfigs = ['fdh_ieee_rv32gc', 'fdqh_ieee_rv32gc', 'fdq_ieee_rv32gc', \ + 'fh_ieee_v32gc', 'f_ieee_rv64gc', 'fdqh_ieee_rv64gc', \ + 'fdq_ieee_rv64gc', 'div_2_1_rv32gc', 'div_2_2_rv32gc', \ + 'div_2_4_rv32gc', 'div_4_1_rv32gc', 'div_4_2_rv32gc', \ + 'div_4_4_rv32gc', 'fd_ieee_rv32gc', 'fh_ieee_rv32gc', \ + 'div_2_1_rv64gc', 'div_2_2_rv64gc', 'div_2_4_rv64gc', \ + 'div_4_1_rv64gc', 'div_4_2_rv64gc', 'div_4_4_rv64gc', \ + 'fd_ieee_rv64gc', 'fh_ieee_rv64gc', 'f_ieee_rv32gc'] + for config in softfloatconfigs: + # div test case + divtest = TestCase( + name="div", + variant=config, + cmd="vsim > {} -c < {} -c < {} -c < {} -c < Date: Tue, 20 Feb 2024 17:17:45 -0800 Subject: [PATCH 05/10] typo fix --- sim/regression-wally | 1 - 1 file changed, 1 deletion(-) diff --git a/sim/regression-wally b/sim/regression-wally index 61f133fa9..b721d8899 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -200,7 +200,6 @@ if (nightly): ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]], ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]], ] - """ derivconfigtests = [ ["tlb2_rv32gc", ["wally32priv"]], ["tlb16_rv32gc", ["wally32priv"]], From c8ff1bddec4bb87aae060c9b9da6094871bff55b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 20 Feb 2024 17:21:29 -0800 Subject: [PATCH 06/10] formatting --- addins/riscv-arch-test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 8a52b016d..c955abf75 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d +Subproject commit c955abf757df98cf38809e40a62d2a6b448ea507 From 7e3df23f28c202a8eaf0aaa67e539e1c32c45fc4 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 20 Feb 2024 17:24:04 -0800 Subject: [PATCH 07/10] Revert "formatting" This reverts commit c8ff1bddec4bb87aae060c9b9da6094871bff55b. --- addins/riscv-arch-test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index c955abf75..8a52b016d 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit c955abf757df98cf38809e40a62d2a6b448ea507 +Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d From 19a61e301ea4a1aea3382225b6fdd017c054d088 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 20 Feb 2024 17:24:15 -0800 Subject: [PATCH 08/10] formatting --- sim/regression-wally | 39 --------------------------------------- 1 file changed, 39 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index b721d8899..28c2e9a7a 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -162,44 +162,6 @@ for test in tests64gc: # run derivative configurations if requested if (nightly): - derivconfigtests = [ - ["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]], - ["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - ["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]], - - - ["f_rv32gc", ["arch32f", "arch32f_divsqrt"]], - ["fh_rv32gc", ["arch32f", "arch32f_divsqrt"]], - ["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32d", "arch32d_divsqrt"]], - ["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32d", "arch32d_divsqrt" ]], - ["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32d", "arch32d_divsqrt"]], - ["f_rv64gc", ["arch64f", "arch64f_divsqrt"]], - ["fh_rv64gc", ["arch64f", "arch64f_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed - ["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]], - ["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]], - ["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64d", "arch64d_divsqrt"]], - ] derivconfigtests = [ ["tlb2_rv32gc", ["wally32priv"]], ["tlb16_rv32gc", ["wally32priv"]], @@ -306,7 +268,6 @@ if (nightly): ["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], ["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"], - # enable floating-point tests when lint is fixed ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]], ["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]], From 02081cac409fec665c0ed0de29648f8dbbca4fb4 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 21 Feb 2024 20:49:38 -0800 Subject: [PATCH 09/10] softfloat jobs now run concurrently with help of testfloat-batch.do directing compiled designs into individual folders for each config/test --- sim/regression-wally | 15 +++++++----- sim/testfloat-batch.do | 55 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+), 6 deletions(-) create mode 100644 sim/testfloat-batch.do diff --git a/sim/regression-wally b/sim/regression-wally index 28c2e9a7a..e53ebd0d8 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -326,7 +326,7 @@ if (softfloat): divtest = TestCase( name="div", variant=config, - cmd="vsim > {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < Date: Thu, 22 Feb 2024 10:22:23 -0800 Subject: [PATCH 10/10] updated configs list in regression-wally --- sim/regression-wally | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index e53ebd0d8..ad1720004 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -321,6 +321,32 @@ if (softfloat): 'div_2_1_rv64gc', 'div_2_2_rv64gc', 'div_2_4_rv64gc', \ 'div_4_1_rv64gc', 'div_4_2_rv64gc', 'div_4_4_rv64gc', \ 'fd_ieee_rv64gc', 'fh_ieee_rv64gc', 'f_ieee_rv32gc'] + softfloatconfigs = ['fdh_ieee_div_2_1_rv32gc', 'fdh_ieee_div_2_1_rv64gc', \ + 'fdh_ieee_div_2_2_rv32gc', 'fdh_ieee_div_2_2_rv64gc', 'fdh_ieee_div_2_4_rv32gc', \ + 'fdh_ieee_div_2_4_rv64gc', 'fdh_ieee_div_4_1_rv32gc', 'fdh_ieee_div_4_1_rv64gc', \ + 'fdh_ieee_div_4_2_rv32gc', 'fdh_ieee_div_4_2_rv64gc', 'fdh_ieee_div_4_4_rv64gc', \ + 'fdh_ieee_rv32gc', 'fd_ieee_div_2_1_rv32gc', 'fd_ieee_div_2_1_rv64gc', \ + 'fd_ieee_div_2_2_rv32gc', 'fd_ieee_div_2_2_rv64gc', 'fd_ieee_div_2_4_rv32gc', \ + 'fd_ieee_div_2_4_rv64gc', 'fd_ieee_div_4_1_rv32gc', 'fd_ieee_div_4_1_rv64gc', \ + 'fd_ieee_div_4_2_rv32gc', 'fd_ieee_div_4_2_rv64gc', 'fd_ieee_div_4_4_rv64gc', \ + 'fd_ieee_rv32gc', 'fd_ieee_rv64gc', 'fdqh_ieee_div_2_1_rv32gc', \ + 'fdqh_ieee_div_2_1_rv64gc', 'fdqh_ieee_div_2_2_rv32gc', 'fdqh_ieee_div_2_2_rv64gc', \ + 'fdqh_ieee_div_2_4_rv32gc', 'fdqh_ieee_div_2_4_rv64gc', 'fdqh_ieee_div_4_1_rv32gc', \ + 'fdqh_ieee_div_4_1_rv64gc', 'fdqh_ieee_div_4_2_rv32gc', 'fdqh_ieee_div_4_2_rv64gc',\ + 'fdqh_ieee_div_4_4_rv64gc', 'fdqh_ieee_rv32gc', 'fdqh_ieee_rv64gc', \ + 'fdq_ieee_div_2_1_rv32gc', 'fdq_ieee_div_2_1_rv64gc', 'fdq_ieee_div_2_2_rv32gc',\ + 'fdq_ieee_div_2_2_rv64gc', 'fdq_ieee_div_2_4_rv32gc', 'fdq_ieee_div_2_4_rv64gc', \ + 'fdq_ieee_div_4_1_rv32gc', 'fdq_ieee_div_4_1_rv64gc', 'fdq_ieee_div_4_2_rv32gc', \ + 'fdq_ieee_div_4_2_rv64gc', 'fdq_ieee_div_4_4_rv64gc', 'fdq_ieee_rv32gc', \ + 'fdq_ieee_rv64gc', 'fh_ieee_div_2_1_rv32gc', 'fh_ieee_div_2_1_rv64gc', \ + 'fh_ieee_div_2_2_rv32gc', 'fh_ieee_div_2_2_rv64gc', 'fh_ieee_div_2_4_rv32gc',\ + 'fh_ieee_div_2_4_rv64gc', 'fh_ieee_div_4_1_rv32gc', 'fh_ieee_div_4_1_rv64gc',\ + 'fh_ieee_div_4_2_rv32gc', 'fh_ieee_div_4_2_rv64gc', 'fh_ieee_div_4_4_rv64gc', \ + 'fh_ieee_rv32gc', 'fh_ieee_rv64gc', 'fh_ieee_v32gc', 'f_ieee_div_2_1_rv32gc', \ + 'f_ieee_div_2_1_rv64gc', 'f_ieee_div_2_2_rv32gc', 'f_ieee_div_2_2_rv64gc', \ + 'f_ieee_div_2_4_rv32gc', 'f_ieee_div_2_4_rv64gc', 'f_ieee_div_4_1_rv32gc', \ + 'f_ieee_div_4_1_rv64gc', 'f_ieee_div_4_2_rv32gc', 'f_ieee_div_4_2_rv64gc', \ + 'f_ieee_div_4_4_rv64gc', 'f_ieee_rv32gc', 'f_ieee_rv64gc'] for config in softfloatconfigs: # div test case divtest = TestCase( @@ -329,7 +355,7 @@ if (softfloat): cmd="vsim > {} -c <