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https://github.com/openhwgroup/cvw
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Add misaligned cjal and cjalr tests
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9711cc7348
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@ -223,7 +223,6 @@ module testbench;
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"arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd;
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"arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd;
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"arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne;
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"arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne;
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"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
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"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
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"arch32c_misalign": if (P.C_SUPPORTED) tests = arch32c_misalign;
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endcase
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endcase
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end
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end
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if (tests.size() == 0 & ElfFile == "none") begin
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if (tests.size() == 0 & ElfFile == "none") begin
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@ -397,7 +397,9 @@ string arch64c[] = '{
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"rv64i_m/C/src/csubw-01.S",
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"rv64i_m/C/src/csubw-01.S",
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"rv64i_m/C/src/csw-01.S",
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"rv64i_m/C/src/csw-01.S",
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"rv64i_m/C/src/cswsp-01.S",
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"rv64i_m/C/src/cswsp-01.S",
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"rv64i_m/C/src/cxor-01.S"
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"rv64i_m/C/src/cxor-01.S",
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"rv64i_m/C/src/misalign1-cjalr-01.S",
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"rv64i_m/C/src/misalign1-cjr-01.S"
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};
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};
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string arch64cpriv[] = '{
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string arch64cpriv[] = '{
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@ -3220,11 +3222,7 @@ string arch32c[] = '{
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"rv32i_m/C/src/csub-01.S",
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"rv32i_m/C/src/csub-01.S",
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"rv32i_m/C/src/csw-01.S",
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"rv32i_m/C/src/csw-01.S",
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"rv32i_m/C/src/cswsp-01.S",
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"rv32i_m/C/src/cswsp-01.S",
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"rv32i_m/C/src/cxor-01.S"
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"rv32i_m/C/src/cxor-01.S",
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};
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string arch32c_misalign[] = '{
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`RISCVARCHTEST,
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"rv32i_m/C/src/misalign1-cjalr-01.S",
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"rv32i_m/C/src/misalign1-cjalr-01.S",
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"rv32i_m/C/src/misalign1-cjr-01.S"
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"rv32i_m/C/src/misalign1-cjr-01.S"
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};
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};
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