From 23f037e76e8897ec858f73243182470f3450a1c8 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sun, 29 Sep 2024 22:33:11 -0700
Subject: [PATCH] Add misaligned cjal and cjalr tests

---
 testbench/testbench.sv |  1 -
 testbench/tests.vh     | 10 ++++------
 2 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index f772a6e2f..46c08fc86 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -223,7 +223,6 @@ module testbench;
         "arch32zknd":    if (P.ZKND_SUPPORTED)    tests = arch32zknd;
         "arch32zkne":    if (P.ZKNE_SUPPORTED)    tests = arch32zkne;
         "arch32zknh":    if (P.ZKNH_SUPPORTED)    tests = arch32zknh;
-        "arch32c_misalign": if (P.C_SUPPORTED)    tests = arch32c_misalign;
       endcase
     end
     if (tests.size() == 0 & ElfFile == "none") begin
diff --git a/testbench/tests.vh b/testbench/tests.vh
index f808e87eb..22241f876 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -397,7 +397,9 @@ string arch64c[] = '{
   "rv64i_m/C/src/csubw-01.S",
   "rv64i_m/C/src/csw-01.S",
   "rv64i_m/C/src/cswsp-01.S",
-  "rv64i_m/C/src/cxor-01.S"
+  "rv64i_m/C/src/cxor-01.S",
+  "rv64i_m/C/src/misalign1-cjalr-01.S",
+  "rv64i_m/C/src/misalign1-cjr-01.S"
 };
 
 string arch64cpriv[] = '{
@@ -3220,11 +3222,7 @@ string arch32c[] = '{
   "rv32i_m/C/src/csub-01.S",
   "rv32i_m/C/src/csw-01.S",
   "rv32i_m/C/src/cswsp-01.S",
-  "rv32i_m/C/src/cxor-01.S"
-};
-
-string arch32c_misalign[] = '{
-  `RISCVARCHTEST,
+  "rv32i_m/C/src/cxor-01.S",
   "rv32i_m/C/src/misalign1-cjalr-01.S",
   "rv32i_m/C/src/misalign1-cjr-01.S"
 };