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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally

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This commit is contained in:
David Harris 2022-07-06 23:43:05 +00:00
commit 21fb120aac
3 changed files with 6 additions and 6 deletions
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3
pipelined/src/cache/cache.sv vendored
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@ -185,7 +185,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER
flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn), flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn),
.val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay)); .val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay));
assign FlushWayFlag = FlushWay[NUMWAYS-1]; assign FlushWayFlag = FlushWay[NUMWAYS-1];
assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; if(NUMWAYS > 1) assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
else assign NextFlushWay = FlushWay[NUMWAYS-1];
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Write Path: Write Enables // Write Path: Write Enables

4
pipelined/src/cache/cachereplacementpolicy.sv vendored
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@ -59,8 +59,8 @@ module cachereplacementpolicy
// Replacement Bits: Register file // Replacement Bits: Register file
// Needs to be resettable for simulation, but could omit reset for synthesis *** // Needs to be resettable for simulation, but could omit reset for synthesis ***
always_ff @(posedge clk) always_ff @(posedge clk)
if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] = '0; if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] <= '0;
else if (LRUWriteEnD) ReplacementBits[RAdrD] = NewReplacementD; else if (LRUWriteEnD) ReplacementBits[RAdrD] <= NewReplacementD;
assign LineReplacementBits = ReplacementBits[RAdrD]; assign LineReplacementBits = ReplacementBits[RAdrD];
genvar index; genvar index;

5
pipelined/src/ifu/ifu.sv
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@ -185,11 +185,10 @@ module ifu (
logic [`XLEN-1:0] AllInstrRawF; logic [`XLEN-1:0] AllInstrRawF;
assign InstrRawF = AllInstrRawF[31:0]; assign InstrRawF = AllInstrRawF[31:0];
if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM
dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill), dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM({{(`XLEN-32){1'b0}}, PCPF[31:0]}), .IEUAdrE(PCNextFSpill),
.TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0), .TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0),
.ReadDataWordM(FinalInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), .ReadDataWordM({{(`XLEN-32){1'b0}}, FinalInstrRawF}), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
.BusCommittedM(), .DCacheStallM(ICacheStallF), .Cacheable(CacheableF), .BusCommittedM(), .DCacheStallM(ICacheStallF), .Cacheable(CacheableF),
.DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess)); .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));