From ad29e19a27303a7562641c775cb266565e2b0f41 Mon Sep 17 00:00:00 2001
From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com>
Date: Wed, 6 Jul 2022 22:39:35 +0000
Subject: [PATCH 1/2] fixed width mismatch for rv64 ieuadrM and readdatawordM

---
 pipelined/src/ifu/ifu.sv | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 02e748f31..0c43c736d 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -185,11 +185,10 @@ module ifu (
   logic [`XLEN-1:0] AllInstrRawF;
   assign InstrRawF = AllInstrRawF[31:0];
 
-  
   if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name.  Probably use a ROM rather than DTIM
-    dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill),
+    dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM({{(`XLEN-32){1'b0}}, PCPF[31:0]}), .IEUAdrE(PCNextFSpill),
               .TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0),
-              .ReadDataWordM(FinalInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
+              .ReadDataWordM({{(`XLEN-32){1'b0}}, FinalInstrRawF}), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
               .BusCommittedM(), .DCacheStallM(ICacheStallF), .Cacheable(CacheableF),
               .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
     

From d716c25275d3586752b173c5aa5dd130684f71bb Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 6 Jul 2022 18:34:30 -0500
Subject: [PATCH 2/2] Fixed an issue with direct map cache's nextway logic.
 Also found a small error in the replacement policy.

---
 pipelined/src/cache/cache.sv                  | 3 ++-
 pipelined/src/cache/cachereplacementpolicy.sv | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index 7f5d2de7a..f6aad78e7 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -185,7 +185,8 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGWPL, WORDLEN, MUXINTER
   flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn), 
     .val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay));
   assign FlushWayFlag = FlushWay[NUMWAYS-1];
-  assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
+  if(NUMWAYS > 1) assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
+  else assign NextFlushWay = FlushWay[NUMWAYS-1];
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Write Path: Write Enables
diff --git a/pipelined/src/cache/cachereplacementpolicy.sv b/pipelined/src/cache/cachereplacementpolicy.sv
index cb33480dc..d407bc284 100644
--- a/pipelined/src/cache/cachereplacementpolicy.sv
+++ b/pipelined/src/cache/cachereplacementpolicy.sv
@@ -59,8 +59,8 @@ module cachereplacementpolicy
   // Replacement Bits: Register file
   // Needs to be resettable for simulation, but could omit reset for synthesis ***
   always_ff @(posedge clk) 
-    if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] = '0;
-    else if (LRUWriteEnD) ReplacementBits[RAdrD] = NewReplacementD;
+    if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] <= '0;
+    else if (LRUWriteEnD) ReplacementBits[RAdrD] <= NewReplacementD;
   assign LineReplacementBits = ReplacementBits[RAdrD];
 
   genvar 		      index;