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Untested change to uart test for outline of how to handle rx fifo timeout.

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This commit is contained in:
Ross Thompson 2022-10-28 13:31:16 -05:00
parent 9f41e57f03
commit 21eca47d2e
1 changed files with 7 additions and 0 deletions
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7
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
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@ -1073,9 +1073,16 @@ uart_data_wait:
li a4, 0x61 li a4, 0x61
uart_read_LSR_IIR: uart_read_LSR_IIR:
lb t4, 0(t3) // save IIR before reading LSR mgith clear it lb t4, 0(t3) // save IIR before reading LSR mgith clear it
// check if t4 is the rxfifotime out interrupt if it is then read the fifo then go back and repeat this.
li t7, 6
beq t4, t7, uart_rxfifo_timout
lb t5, 0(t2) // read LSR lb t5, 0(t2) // read LSR
andi t6, t5, 0x61 // wait until all transmissions are done and data is ready andi t6, t5, 0x61 // wait until all transmissions are done and data is ready
bne a4, t6, uart_read_LSR_IIR bne a4, t6, uart_read_LSR_IIR
uart_rxfifo_timout:
//read the fifo until empty
j uart_read_LSR_IIR
uart_data_ready: uart_data_ready:
li t2, 0 li t2, 0