diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
index 7146e8334..1293d23ad 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
@@ -1073,9 +1073,16 @@ uart_data_wait:
     li a4, 0x61
 uart_read_LSR_IIR:
     lb t4, 0(t3) // save IIR before reading LSR mgith clear it
+//  check if t4 is the rxfifotime out interrupt if it is then read the fifo then go back and repeat this.
+    li t7, 6
+    beq t4, t7, uart_rxfifo_timout
     lb t5, 0(t2) // read LSR
     andi t6, t5, 0x61  // wait until all transmissions are done and data is ready
     bne a4, t6, uart_read_LSR_IIR
+uart_rxfifo_timout:
+//read the fifo until empty
+   j uart_read_LSR_IIR
+
 
 uart_data_ready:
     li t2, 0