mmu cleanup

pipelined/src/mmu/tlbcontrol.sv

@@ -29,18 +29,11 @@
 `include "wally-config.vh"
 
 module tlbcontrol #(parameter ITLB = 0) (
-
-  // Current value of satp CSR (from privileged unit)
   input  logic [`SVMODE_BITS-1:0] SATP_MODE,
   input  logic [`XLEN-1:0]        VAdr,
   input  logic                    STATUS_MXR, STATUS_SUM, STATUS_MPRV,
   input  logic [1:0]              STATUS_MPP,
   input  logic [1:0]              PrivilegeModeW, // Current privilege level of the processeor
-
-  // 00 - TLB is not being accessed
-  // 1x - TLB is accessed for a read (or an instruction)
-  // x1 - TLB is accessed for a write
-  // 11 - TLB is accessed for both read and write
   input  logic                    ReadAccess, WriteAccess,
   input  logic                    DisableTranslation,
   input  logic                    TLBFlush, // Invalidate all TLB entries
@@ -70,8 +63,12 @@ module tlbcontrol #(parameter ITLB = 0) (
   // Determine whether TLB is being used
   assign TLBAccess = ReadAccess | WriteAccess;
 
-  // Check whether upper bits of virtual addresss are all equal
+  if (`XLEN==64) // Check whether upper bits of 64-bit virtual addressses are all equal
     vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequalPageFault);
+  else begin
+    assign SV39Mode = 0;
+    assign UpperBitsUnequalPageFault = 0;
+  end           
 
   // unswizzle useful PTE bits
   assign {PTE_D, PTE_A} = PTEAccessBits[7:6];

pipelined/src/mmu/vm64check.sv

@@ -31,18 +31,16 @@
 module vm64check (
   input  logic [`SVMODE_BITS-1:0] SATP_MODE,
   input  logic [`XLEN-1:0]        VAdr,
-   output logic                    SV39Mode, UpperBitsUnequalPageFault
+  output logic                    SV39Mode, 
+  output logic                    UpperBitsUnequalPageFault
 );
 
-  if (`XLEN==64) begin:rv64
+  logic                           eq_63_47, eq_46_38;
+
   assign SV39Mode = (SATP_MODE == `SV39);
+
   // page fault if upper bits aren't all the same
-      logic UpperEqual39, UpperEqual48;
-      assign UpperEqual39 = &(VAdr[63:38]) | ~|(VAdr[63:38]);
-      assign UpperEqual48 = &(VAdr[63:47]) | ~|(VAdr[63:47]); 
-      assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48;
-  end else begin
-      assign SV39Mode = 0;
-      assign UpperBitsUnequalPageFault = 0;
-  end           
+  assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]);
+  assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); 
+  assign UpperBitsUnequalPageFault = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
 endmodule