diff --git a/pipelined/src/mmu/tlbcontrol.sv b/pipelined/src/mmu/tlbcontrol.sv index 7c4b50aa2..1561b2394 100644 --- a/pipelined/src/mmu/tlbcontrol.sv +++ b/pipelined/src/mmu/tlbcontrol.sv @@ -29,39 +29,32 @@ `include "wally-config.vh" module tlbcontrol #(parameter ITLB = 0) ( - - // Current value of satp CSR (from privileged unit) - input logic [`SVMODE_BITS-1:0] SATP_MODE, - input logic [`XLEN-1:0] VAdr, - input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, - input logic [1:0] STATUS_MPP, - input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor - - // 00 - TLB is not being accessed - // 1x - TLB is accessed for a read (or an instruction) - // x1 - TLB is accessed for a write - // 11 - TLB is accessed for both read and write - input logic ReadAccess, WriteAccess, - input logic DisableTranslation, - input logic TLBFlush, // Invalidate all TLB entries - input logic [7:0] PTEAccessBits, - input logic CAMHit, - input logic Misaligned, - output logic TLBMiss, - output logic TLBHit, - output logic TLBPageFault, - output logic DAPageFault, - output logic SV39Mode, - output logic Translate + input logic [`SVMODE_BITS-1:0] SATP_MODE, + input logic [`XLEN-1:0] VAdr, + input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, + input logic [1:0] STATUS_MPP, + input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor + input logic ReadAccess, WriteAccess, + input logic DisableTranslation, + input logic TLBFlush, // Invalidate all TLB entries + input logic [7:0] PTEAccessBits, + input logic CAMHit, + input logic Misaligned, + output logic TLBMiss, + output logic TLBHit, + output logic TLBPageFault, + output logic DAPageFault, + output logic SV39Mode, + output logic Translate ); // Sections of the page table entry - logic [1:0] EffectivePrivilegeMode; + logic [1:0] EffectivePrivilegeMode; - logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits - logic UpperBitsUnequalPageFault; - logic TLBAccess; - logic ImproperPrivilege; + logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits + logic UpperBitsUnequalPageFault; + logic TLBAccess; + logic ImproperPrivilege; // Grab the sv mode from SATP and determine whether translation should occur assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1 @@ -70,8 +63,12 @@ module tlbcontrol #(parameter ITLB = 0) ( // Determine whether TLB is being used assign TLBAccess = ReadAccess | WriteAccess; - // Check whether upper bits of virtual addresss are all equal - vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequalPageFault); + if (`XLEN==64) // Check whether upper bits of 64-bit virtual addressses are all equal + vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequalPageFault); + else begin + assign SV39Mode = 0; + assign UpperBitsUnequalPageFault = 0; + end // unswizzle useful PTE bits assign {PTE_D, PTE_A} = PTEAccessBits[7:6]; diff --git a/pipelined/src/mmu/tlblru.sv b/pipelined/src/mmu/tlblru.sv index 9d4449f2e..6cdb475e3 100644 --- a/pipelined/src/mmu/tlblru.sv +++ b/pipelined/src/mmu/tlblru.sv @@ -28,18 +28,18 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module tlblru #(parameter TLB_ENTRIES = 8) ( - input logic clk, reset, - input logic TLBWrite, - input logic TLBFlush, - input logic [TLB_ENTRIES-1:0] Matches, - input logic CAMHit, - output logic [TLB_ENTRIES-1:0] WriteEnables + input logic clk, reset, + input logic TLBWrite, + input logic TLBFlush, + input logic [TLB_ENTRIES-1:0] Matches, + input logic CAMHit, + output logic [TLB_ENTRIES-1:0] WriteEnables ); - logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed; - logic [TLB_ENTRIES-1:0] WriteLines; - logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed - logic AllUsed; // High if the next access causes all RU bits to be 1 + logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed; + logic [TLB_ENTRIES-1:0] WriteLines; + logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed + logic AllUsed; // High if the next access causes all RU bits to be 1 // Find the first line not recently used priorityonehot #(TLB_ENTRIES) nru(.a(~RUBits), .y(WriteLines)); diff --git a/pipelined/src/mmu/vm64check.sv b/pipelined/src/mmu/vm64check.sv index 549ab83c2..975890d9f 100644 --- a/pipelined/src/mmu/vm64check.sv +++ b/pipelined/src/mmu/vm64check.sv @@ -29,20 +29,18 @@ `include "wally-config.vh" module vm64check ( - input logic [`SVMODE_BITS-1:0] SATP_MODE, - input logic [`XLEN-1:0] VAdr, - output logic SV39Mode, UpperBitsUnequalPageFault + input logic [`SVMODE_BITS-1:0] SATP_MODE, + input logic [`XLEN-1:0] VAdr, + output logic SV39Mode, + output logic UpperBitsUnequalPageFault ); - if (`XLEN==64) begin:rv64 - assign SV39Mode = (SATP_MODE == `SV39); - // page fault if upper bits aren't all the same - logic UpperEqual39, UpperEqual48; - assign UpperEqual39 = &(VAdr[63:38]) | ~|(VAdr[63:38]); - assign UpperEqual48 = &(VAdr[63:47]) | ~|(VAdr[63:47]); - assign UpperBitsUnequalPageFault = SV39Mode ? ~UpperEqual39 : ~UpperEqual48; - end else begin - assign SV39Mode = 0; - assign UpperBitsUnequalPageFault = 0; - end + logic eq_63_47, eq_46_38; + + assign SV39Mode = (SATP_MODE == `SV39); + + // page fault if upper bits aren't all the same + assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]); + assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); + assign UpperBitsUnequalPageFault = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; endmodule