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Supress misaligned faults during a tlb miss. Still needs to be tested.
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@ -138,8 +138,8 @@ module mmu import cvw::*; #(parameter cvw_t P,
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2'b11: DataMisalignedM = |VAdr[2:0]; // ld, sd, fld, fsd
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2'b11: DataMisalignedM = |VAdr[2:0]; // ld, sd, fld, fsd
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endcase
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endcase
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// When ZiCCLSM_SUPPORTED, misalgined cachable loads and stores are handled in hardware so they do not throw a misaligned fault
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// When ZiCCLSM_SUPPORTED, misalgined cachable loads and stores are handled in hardware so they do not throw a misaligned fault
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assign LoadMisalignedFaultM = DataMisalignedM & ReadNoAmoAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable);
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assign LoadMisalignedFaultM = DataMisalignedM & ReadNoAmoAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss;
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assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable); // Store and AMO both assert WriteAccess
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assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss; // Store and AMO both assert WriteAccess
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// Access faults
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// Access faults
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// If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
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// If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
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