From 2112c705a4a064c51c7383c67be9dac8f7574f9b Mon Sep 17 00:00:00 2001
From: Rose Thompson <rose@rosethompson.net>
Date: Mon, 30 Sep 2024 15:55:46 -0500
Subject: [PATCH] Supress misaligned faults during a tlb miss. Still needs to
 be tested.

---
 src/mmu/mmu.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv
index 9130dc3d4..85796f060 100644
--- a/src/mmu/mmu.sv
+++ b/src/mmu/mmu.sv
@@ -138,8 +138,8 @@ module mmu import cvw::*;  #(parameter cvw_t P,
       2'b11:  DataMisalignedM = |VAdr[2:0];        // ld, sd, fld, fsd
     endcase 
   // When ZiCCLSM_SUPPORTED, misalgined cachable loads and stores are handled in hardware so they do not throw a misaligned fault
-  assign LoadMisalignedFaultM     = DataMisalignedM & ReadNoAmoAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable); 
-  assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable); // Store and AMO both assert WriteAccess
+  assign LoadMisalignedFaultM     = DataMisalignedM & ReadNoAmoAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss; 
+  assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss; // Store and AMO both assert WriteAccess
 
   // Access faults
   // If TLB miss and translating we want to not have faults from the PMA and PMP checkers.