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Simplified ALU and source multiplexers pass tests

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This commit is contained in:
David Harris 2021-12-13 07:57:38 -08:00
parent a7e9dee77d
commit 2039752740
7 changed files with 11 additions and 8 deletions
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2
wally-pipelined/regression/sim-wally
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@ -1,2 +1,2 @@
vsim -do "do wally-pipelined.do rv32g arch32i" vsim -do "do wally-pipelined.do rv64g arch64i"

2
wally-pipelined/regression/sim-wally-batch
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@ -1,3 +1,3 @@
vsim -c <<! vsim -c <<!
do wally-pipelined-batch.do rv32g arch32f do wally-pipelined-batch.do rv64g arch64i
! !

2
wally-pipelined/src/ebu/amoalu.sv
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@ -25,6 +25,8 @@
`include "wally-config.vh" `include "wally-config.vh"
// *** this should probably be moved into the LSU because it is instantiated in the D$
module amoalu ( module amoalu (
input logic [`XLEN-1:0] srca, srcb, input logic [`XLEN-1:0] srca, srcb,
input logic [6:0] funct, input logic [6:0] funct,

2
wally-pipelined/src/ieu/comparator.sv
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@ -37,7 +37,7 @@ module comparator #(parameter WIDTH=32) (
// subtraction // subtraction
assign bbar = ~b; assign bbar = ~b;
assign {carry, diff} = a + bbar; assign {carry, diff} = a + bbar + 1;
// condition code flags based on add/subtract output // condition code flags based on add/subtract output
assign zero = (diff == 0); assign zero = (diff == 0);

6
wally-pipelined/src/ieu/controller.sv
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@ -145,9 +145,9 @@ module controller(
else else
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
//7'b1010011: ControlsD = `CTRLW'b0_000_00_00_101_0_00_0_0_0_0_0_0_0_00_1; // FP //7'b1010011: ControlsD = `CTRLW'b0_000_00_00_101_0_00_0_0_0_0_0_0_0_00_1; // FP
7'b1100011: ControlsD = `CTRLW'b0_010_00_00_000_1_0_0_0_0_0_0_0_0_00_0; // beq 7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches
7'b1100111: ControlsD = `CTRLW'b1_000_00_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr 7'b1100111: ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
7'b1101111: ControlsD = `CTRLW'b1_011_00_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal 7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
7'b1110011: if (Funct3D == 3'b000) 7'b1110011: if (Funct3D == 3'b000)
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules
else else

4
wally-pipelined/testbench/common/sdModel.sv
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@ -118,6 +118,8 @@ module sdModel
reg [3:0] crcDat_in; reg [3:0] crcDat_in;
wire [15:0] crcDat_out [3:0]; wire [15:0] crcDat_out [3:0];
integer sdModel_file_desc;
genvar i; genvar i;
generate generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen for(i=0; i<4; i=i+1) begin:CRC_16_gen
@ -1050,8 +1052,6 @@ module sdModel
endcase // case (dataState) endcase // case (dataState)
end // always @ (negedge sdClk) end // always @ (negedge sdClk)
integer sdModel_file_desc;
initial initial
begin begin
sdModel_file_desc = $fopen("sd_model.log"); sdModel_file_desc = $fopen("sd_model.log");

1
wally-pipelined/testbench/tests.vh
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@ -586,6 +586,7 @@ string imperas32f[] = '{
string arch64i[] = '{ string arch64i[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv64i_m/I/beq-01", "47010",
"rv64i_m/I/add-01", "9010", "rv64i_m/I/add-01", "9010",
"rv64i_m/I/addi-01", "6010", "rv64i_m/I/addi-01", "6010",
"rv64i_m/I/addiw-01", "6010", "rv64i_m/I/addiw-01", "6010",