From 2039752740a6ed3fe09d4e070f0af9f9edbe2f4c Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 13 Dec 2021 07:57:38 -0800
Subject: [PATCH] Simplified ALU and source multiplexers pass tests
---
wally-pipelined/regression/sim-wally | 2 +-
wally-pipelined/regression/sim-wally-batch | 2 +-
wally-pipelined/src/ebu/amoalu.sv | 2 ++
wally-pipelined/src/ieu/comparator.sv | 2 +-
wally-pipelined/src/ieu/controller.sv | 6 +++---
wally-pipelined/testbench/common/sdModel.sv | 4 ++--
wally-pipelined/testbench/tests.vh | 1 +
7 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/wally-pipelined/regression/sim-wally b/wally-pipelined/regression/sim-wally
index 0c1182563..d3071bd15 100755
--- a/wally-pipelined/regression/sim-wally
+++ b/wally-pipelined/regression/sim-wally
@@ -1,2 +1,2 @@
-vsim -do "do wally-pipelined.do rv32g arch32i"
+vsim -do "do wally-pipelined.do rv64g arch64i"
diff --git a/wally-pipelined/regression/sim-wally-batch b/wally-pipelined/regression/sim-wally-batch
index 4b627b768..ff9444507 100755
--- a/wally-pipelined/regression/sim-wally-batch
+++ b/wally-pipelined/regression/sim-wally-batch
@@ -1,3 +1,3 @@
vsim -c <<!
-do wally-pipelined-batch.do rv32g arch32f
+do wally-pipelined-batch.do rv64g arch64i
!
diff --git a/wally-pipelined/src/ebu/amoalu.sv b/wally-pipelined/src/ebu/amoalu.sv
index 45f419665..2700dbc34 100644
--- a/wally-pipelined/src/ebu/amoalu.sv
+++ b/wally-pipelined/src/ebu/amoalu.sv
@@ -25,6 +25,8 @@
`include "wally-config.vh"
+// *** this should probably be moved into the LSU because it is instantiated in the D$
+
module amoalu (
input logic [`XLEN-1:0] srca, srcb,
input logic [6:0] funct,
diff --git a/wally-pipelined/src/ieu/comparator.sv b/wally-pipelined/src/ieu/comparator.sv
index 8178d3380..141172744 100644
--- a/wally-pipelined/src/ieu/comparator.sv
+++ b/wally-pipelined/src/ieu/comparator.sv
@@ -37,7 +37,7 @@ module comparator #(parameter WIDTH=32) (
// subtraction
assign bbar = ~b;
- assign {carry, diff} = a + bbar;
+ assign {carry, diff} = a + bbar + 1;
// condition code flags based on add/subtract output
assign zero = (diff == 0);
diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv
index 90ab5af60..02e380a47 100644
--- a/wally-pipelined/src/ieu/controller.sv
+++ b/wally-pipelined/src/ieu/controller.sv
@@ -145,9 +145,9 @@ module controller(
else
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
//7'b1010011: ControlsD = `CTRLW'b0_000_00_00_101_0_00_0_0_0_0_0_0_0_00_1; // FP
- 7'b1100011: ControlsD = `CTRLW'b0_010_00_00_000_1_0_0_0_0_0_0_0_0_00_0; // beq
- 7'b1100111: ControlsD = `CTRLW'b1_000_00_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
- 7'b1101111: ControlsD = `CTRLW'b1_011_00_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
+ 7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches
+ 7'b1100111: ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
+ 7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
7'b1110011: if (Funct3D == 3'b000)
ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules
else
diff --git a/wally-pipelined/testbench/common/sdModel.sv b/wally-pipelined/testbench/common/sdModel.sv
index a6c36f1fd..741d741e0 100644
--- a/wally-pipelined/testbench/common/sdModel.sv
+++ b/wally-pipelined/testbench/common/sdModel.sv
@@ -118,6 +118,8 @@ module sdModel
reg [3:0] crcDat_in;
wire [15:0] crcDat_out [3:0];
+ integer sdModel_file_desc;
+
genvar i;
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen
@@ -1050,8 +1052,6 @@ module sdModel
endcase // case (dataState)
end // always @ (negedge sdClk)
- integer sdModel_file_desc;
-
initial
begin
sdModel_file_desc = $fopen("sd_model.log");
diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh
index a12f96991..ec3a53157 100644
--- a/wally-pipelined/testbench/tests.vh
+++ b/wally-pipelined/testbench/tests.vh
@@ -586,6 +586,7 @@ string imperas32f[] = '{
string arch64i[] = '{
`RISCVARCHTEST,
+ "rv64i_m/I/beq-01", "47010",
"rv64i_m/I/add-01", "9010",
"rv64i_m/I/addi-01", "6010",
"rv64i_m/I/addiw-01", "6010",