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Removed EarlyTermShift from fdiv

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This commit is contained in:
David Harris 2022-09-19 08:44:23 -07:00
parent a36747fda0
commit 1e6bd26bb6
7 changed files with 11 additions and 24 deletions
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6
pipelined/src/fpu/divshiftcalc.sv
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@ -4,7 +4,6 @@ module divshiftcalc(
input logic [`DIVb-(`RADIX/4):0] DivQm,
input logic [`FMTBITS-1:0] Fmt,
input logic Sqrt,
input logic [`DURLEN-1:0] DivEarlyTermShift,
input logic [`NE+1:0] DivQe,
output logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt,
output logic [`NORMSHIFTSZ-1:0] DivShiftIn,
@ -13,6 +12,8 @@ module divshiftcalc(
);
logic [`NE+1:0] NormShift;
logic [`DURLEN-1:0] DivEarlyTermShift = 0;
// is the result denromalized
// if the exponent is 1 then the result needs to be normalized then the result is denormalizes
assign DivResDenorm = DivQe[`NE+1]|(~|DivQe[`NE+1:0]);
@ -35,7 +36,8 @@ module divshiftcalc(
assign NormShift = (`NE+2)'(`NF);
// if the shift amount is negitive then dont shift (keep sticky bit)
// need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES)
assign DivShiftAmt = (DivResDenorm ? DivDenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DivDenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0])+{{$clog2(`NORMSHIFTSZ)-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}}, DivEarlyTermShift&{`DURLEN{~(DivDenormShift[`NE+1]|Sqrt)}}, {$clog2(`LOGR*`DIVCOPIES){1'b0}}};
assign DivShiftAmt = (DivResDenorm ? DivDenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DivDenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0])+{{$clog2(`NORMSHIFTSZ)-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}},
DivEarlyTermShift&{`DURLEN{~(DivDenormShift[`NE+1]|Sqrt)}}, {$clog2(`LOGR*`DIVCOPIES){1'b0}}};
assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1+(`RADIX/4)-`NF{1'b0}}};

3
pipelined/src/fpu/fdivsqrt.sv
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@ -48,7 +48,6 @@ module fdivsqrt(
output logic DivBusy,
output logic DivDone,
output logic [`NE+1:0] QeM,
output logic [`DURLEN-1:0] EarlyTermShiftM,
output logic [`DIVb-(`RADIX/4):0] QmM
// output logic [`XLEN-1:0] RemM,
);
@ -70,7 +69,7 @@ module fdivsqrt(
.clk, .reset, .FmtE, .XsE, .SqrtE,
.DivBusy, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
.XNaNE, .YNaNE,
.XInfE, .YInfE, .EarlyTermShiftE(EarlyTermShiftM), .WZero);
.XInfE, .YInfE, .WZero);
fdivsqrtiter fdivsqrtiter(
.clk, .Firstqn, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM,
.X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN,

4
pipelined/src/fpu/fdivsqrtfsm.sv
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@ -43,7 +43,6 @@ module fdivsqrtfsm(
input logic StallE,
input logic StallM,
input logic WZero,
output logic [`DURLEN-1:0] EarlyTermShiftE,
output logic DivDone,
output logic DivBusy
);
@ -55,9 +54,6 @@ module fdivsqrtfsm(
logic SpecialCase;
logic [`DURLEN-1:0] cycles;
assign EarlyTermShiftE = 0; // *** remove this signal when having unified design
// assign EarlyTermShiftE = step;
// terminate immediately on special cases
assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);

9
pipelined/src/fpu/fdivsqrtpostproc.sv
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@ -44,9 +44,9 @@ module fdivsqrtpostproc(
logic [`DIVb+3:0] W;
logic NegSticky;
logic weq0;
// check for early termination on an exact result. If the result is not exact, the sticky should be set
logic weq0;
aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0);
if (`RADIX == 2) begin
@ -73,11 +73,4 @@ module fdivsqrtpostproc(
always_comb
if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0] << SqrtM;
else QmM = FirstU[`DIVb-(`RADIX/4):0] << SqrtM;
/* if(SqrtM) // sqrt ouputs in the range (1, .5]
if(NegSticky) QmM = {FirstUM[`DIVb-1-(`RADIX/4):0], 1'b0};
else QmM = {FirstU[`DIVb-1-(`RADIX/4):0], 1'b0};
else
if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0];
else QmM = FirstU[`DIVb-(`RADIX/4):0]; */
endmodule

5
pipelined/src/fpu/fpu.sv
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@ -127,7 +127,6 @@ module fpu (
logic [`NE+1:0] QeE, QeM;
logic DivSE, DivSM;
logic DivDoneM;
logic [`DURLEN-1:0] EarlyTermShiftM;
// result and flag signals
logic [`XLEN-1:0] ClassResE; // classify result
@ -260,7 +259,7 @@ module fpu (
fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), .XsE,
.StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal
.EarlyTermShiftM, .QmM, .DivDone(DivDoneM));
.QmM, .DivDone(DivDoneM));
// compare
// - fmin/fmax
// - flt/fle/feq
@ -364,7 +363,7 @@ module fpu (
assign FpLoadStoreM = FResSelM[1];
postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM), .DivEarlyTermShift(EarlyTermShiftM),
postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM),
.FmaZmS(ZmStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
.ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), .DivDone(DivDoneM),
.FmaNegSum(NegSumM), .FmaInvA(InvAM), .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),

3
pipelined/src/fpu/postprocess.sv
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@ -56,7 +56,6 @@ module postprocess (
input logic FmaSs,
input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // the normalization shift count
//divide signals
input logic [`DURLEN-1:0] DivEarlyTermShift,
input logic DivS,
input logic DivDone,
input logic [`NE+1:0] DivQe,
@ -152,7 +151,7 @@ module postprocess (
.XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaPe, .FmaSCnt, .Fmt, .FmaKillProd, .NormSumExp, .FmaSe,
.FmaSZero, .FmaPreResultDenorm, .FmaShiftAmt, .FmaShiftIn);
divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivEarlyTermShift, .DivResDenorm, .DivDenormShift, .DivShiftAmt, .DivShiftIn);
divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivResDenorm, .DivDenormShift, .DivShiftAmt, .DivShiftIn);
always_comb
case(PostProcSel)

5
pipelined/testbench/testbench-fp.sv
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@ -82,7 +82,6 @@ module testbenchfp;
logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
logic [`DIVb-(`RADIX/4):0] Quot;
logic CvtResDenormUfE;
logic [`DURLEN-1:0] EarlyTermShift;
logic DivStart, DivBusy;
logic reset = 1'b0;
logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
@ -701,7 +700,7 @@ module testbenchfp;
.XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal),
.XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero,
.FmaKillProd(KillProd), .FmaZmS(ZmSticky), .FmaPe(Pe), .DivDone, .FmaSe(Se),
.FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaSCnt(SCnt), .DivEarlyTermShift(EarlyTermShift), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal),
.FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal),
.PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));
if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt
@ -719,7 +718,7 @@ module testbenchfp;
fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
.XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart),
.StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp),
.EarlyTermShiftM(EarlyTermShift), .QmM(Quot), .DivDone);
.QmM(Quot), .DivDone);
end
assign CmpFlg[3:0] = 0;