From 1e6bd26bb6e22e5734b1ed48f028ec33fd8d107d Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 19 Sep 2022 08:44:23 -0700 Subject: [PATCH] Removed EarlyTermShift from fdiv --- pipelined/src/fpu/divshiftcalc.sv | 6 ++++-- pipelined/src/fpu/fdivsqrt.sv | 3 +-- pipelined/src/fpu/fdivsqrtfsm.sv | 4 ---- pipelined/src/fpu/fdivsqrtpostproc.sv | 9 +-------- pipelined/src/fpu/fpu.sv | 5 ++--- pipelined/src/fpu/postprocess.sv | 3 +-- pipelined/testbench/testbench-fp.sv | 5 ++--- 7 files changed, 11 insertions(+), 24 deletions(-) diff --git a/pipelined/src/fpu/divshiftcalc.sv b/pipelined/src/fpu/divshiftcalc.sv index 8095b5171..e31d60447 100644 --- a/pipelined/src/fpu/divshiftcalc.sv +++ b/pipelined/src/fpu/divshiftcalc.sv @@ -4,7 +4,6 @@ module divshiftcalc( input logic [`DIVb-(`RADIX/4):0] DivQm, input logic [`FMTBITS-1:0] Fmt, input logic Sqrt, - input logic [`DURLEN-1:0] DivEarlyTermShift, input logic [`NE+1:0] DivQe, output logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt, output logic [`NORMSHIFTSZ-1:0] DivShiftIn, @@ -13,6 +12,8 @@ module divshiftcalc( ); logic [`NE+1:0] NormShift; + logic [`DURLEN-1:0] DivEarlyTermShift = 0; + // is the result denromalized // if the exponent is 1 then the result needs to be normalized then the result is denormalizes assign DivResDenorm = DivQe[`NE+1]|(~|DivQe[`NE+1:0]); @@ -35,7 +36,8 @@ module divshiftcalc( assign NormShift = (`NE+2)'(`NF); // if the shift amount is negitive then dont shift (keep sticky bit) // need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES) - assign DivShiftAmt = (DivResDenorm ? DivDenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DivDenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0])+{{$clog2(`NORMSHIFTSZ)-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}}, DivEarlyTermShift&{`DURLEN{~(DivDenormShift[`NE+1]|Sqrt)}}, {$clog2(`LOGR*`DIVCOPIES){1'b0}}}; + assign DivShiftAmt = (DivResDenorm ? DivDenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DivDenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0])+{{$clog2(`NORMSHIFTSZ)-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}}, + DivEarlyTermShift&{`DURLEN{~(DivDenormShift[`NE+1]|Sqrt)}}, {$clog2(`LOGR*`DIVCOPIES){1'b0}}}; assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1+(`RADIX/4)-`NF{1'b0}}}; diff --git a/pipelined/src/fpu/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt.sv index 54346d65d..7969e0e48 100644 --- a/pipelined/src/fpu/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt.sv @@ -48,7 +48,6 @@ module fdivsqrt( output logic DivBusy, output logic DivDone, output logic [`NE+1:0] QeM, - output logic [`DURLEN-1:0] EarlyTermShiftM, output logic [`DIVb-(`RADIX/4):0] QmM // output logic [`XLEN-1:0] RemM, ); @@ -70,7 +69,7 @@ module fdivsqrt( .clk, .reset, .FmtE, .XsE, .SqrtE, .DivBusy, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .XNaNE, .YNaNE, - .XInfE, .YInfE, .EarlyTermShiftE(EarlyTermShiftM), .WZero); + .XInfE, .YInfE, .WZero); fdivsqrtiter fdivsqrtiter( .clk, .Firstqn, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM, .X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, diff --git a/pipelined/src/fpu/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrtfsm.sv index d3236e8f1..9b0a23146 100644 --- a/pipelined/src/fpu/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrtfsm.sv @@ -43,7 +43,6 @@ module fdivsqrtfsm( input logic StallE, input logic StallM, input logic WZero, - output logic [`DURLEN-1:0] EarlyTermShiftE, output logic DivDone, output logic DivBusy ); @@ -55,9 +54,6 @@ module fdivsqrtfsm( logic SpecialCase; logic [`DURLEN-1:0] cycles; - assign EarlyTermShiftE = 0; // *** remove this signal when having unified design -// assign EarlyTermShiftE = step; - // terminate immediately on special cases assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE); diff --git a/pipelined/src/fpu/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrtpostproc.sv index c882dffa7..e34ed3dbf 100644 --- a/pipelined/src/fpu/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrtpostproc.sv @@ -44,9 +44,9 @@ module fdivsqrtpostproc( logic [`DIVb+3:0] W; logic NegSticky; + logic weq0; // check for early termination on an exact result. If the result is not exact, the sticky should be set - logic weq0; aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0); if (`RADIX == 2) begin @@ -73,11 +73,4 @@ module fdivsqrtpostproc( always_comb if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0] << SqrtM; else QmM = FirstU[`DIVb-(`RADIX/4):0] << SqrtM; -/* if(SqrtM) // sqrt ouputs in the range (1, .5] - if(NegSticky) QmM = {FirstUM[`DIVb-1-(`RADIX/4):0], 1'b0}; - else QmM = {FirstU[`DIVb-1-(`RADIX/4):0], 1'b0}; - else - if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0]; - else QmM = FirstU[`DIVb-(`RADIX/4):0]; */ - endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index bfc6af0e6..48598d560 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -127,7 +127,6 @@ module fpu ( logic [`NE+1:0] QeE, QeM; logic DivSE, DivSM; logic DivDoneM; - logic [`DURLEN-1:0] EarlyTermShiftM; // result and flag signals logic [`XLEN-1:0] ClassResE; // classify result @@ -260,7 +259,7 @@ module fpu ( fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]), .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), .XsE, .StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal - .EarlyTermShiftM, .QmM, .DivDone(DivDoneM)); + .QmM, .DivDone(DivDoneM)); // compare // - fmin/fmax // - flt/fle/feq @@ -364,7 +363,7 @@ module fpu ( assign FpLoadStoreM = FResSelM[1]; - postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM), .DivEarlyTermShift(EarlyTermShiftM), + postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM), .FmaZmS(ZmStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM), .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), .DivDone(DivDoneM), .FmaNegSum(NegSumM), .FmaInvA(InvAM), .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM), diff --git a/pipelined/src/fpu/postprocess.sv b/pipelined/src/fpu/postprocess.sv index 8039f7c37..2b5df8e9e 100644 --- a/pipelined/src/fpu/postprocess.sv +++ b/pipelined/src/fpu/postprocess.sv @@ -56,7 +56,6 @@ module postprocess ( input logic FmaSs, input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // the normalization shift count //divide signals - input logic [`DURLEN-1:0] DivEarlyTermShift, input logic DivS, input logic DivDone, input logic [`NE+1:0] DivQe, @@ -152,7 +151,7 @@ module postprocess ( .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn); fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaPe, .FmaSCnt, .Fmt, .FmaKillProd, .NormSumExp, .FmaSe, .FmaSZero, .FmaPreResultDenorm, .FmaShiftAmt, .FmaShiftIn); - divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivEarlyTermShift, .DivResDenorm, .DivDenormShift, .DivShiftAmt, .DivShiftIn); + divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivResDenorm, .DivDenormShift, .DivShiftAmt, .DivShiftIn); always_comb case(PostProcSel) diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index e96bc55c0..06f810a32 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -82,7 +82,6 @@ module testbenchfp; logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by logic [`DIVb-(`RADIX/4):0] Quot; logic CvtResDenormUfE; - logic [`DURLEN-1:0] EarlyTermShift; logic DivStart, DivBusy; logic reset = 1'b0; logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt; @@ -701,7 +700,7 @@ module testbenchfp; .XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal), .XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero, .FmaKillProd(KillProd), .FmaZmS(ZmSticky), .FmaPe(Pe), .DivDone, .FmaSe(Se), - .FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaSCnt(SCnt), .DivEarlyTermShift(EarlyTermShift), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), + .FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes)); if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt @@ -719,7 +718,7 @@ module testbenchfp; fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]), .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart), .StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp), - .EarlyTermShiftM(EarlyTermShift), .QmM(Quot), .DivDone); + .QmM(Quot), .DivDone); end assign CmpFlg[3:0] = 0;