From 1d811b085c8c03194e8d6b04ed5e1df051ef8093 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 21 Nov 2023 00:14:59 -0600 Subject: [PATCH] More cleanup. --- src/cache/cachefsm.sv | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index edb87f29a..e507f1daa 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -171,13 +171,9 @@ module cachefsm import cvw::*; #(parameter cvw_t P, (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. // Flush and eviction controls (P.ZICBOM_SUPPORTED & CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2]) & CacheBusAck); - assign SelWay = (CurrState == STATE_WRITEBACK & ~CacheBusAck & ~(CMOp[1] | CMOp[2])) | - (CurrState == STATE_READY & AnyMiss & LineDirty) | - (CurrState == STATE_WRITE_LINE) | - // This is almost the same as setvalid, but on cachehit we don't want to select - // the nonhit way, but instead want to force this to zero - (P.ZICBOZ_SUPPORTED & CurrState == STATE_READY & CMOZeroNoEviction & ~CacheHit) | - (P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CacheBusAck & CMOp[3]); + assign SelWay = (CurrState == STATE_WRITEBACK & ((~CacheBusAck & ~(CMOp[1] | CMOp[2])) | (P.ZICBOZ_SUPPORTED & CacheBusAck & CMOp[3]))) | + (CurrState == STATE_READY & ((AnyMiss & LineDirty) | (P.ZICBOZ_SUPPORTED & CMOZeroNoEviction & ~CacheHit))) | + (CurrState == STATE_WRITE_LINE); assign ZeroCacheLine = P.ZICBOZ_SUPPORTED & ((CurrState == STATE_READY & CMOZeroNoEviction) | (CurrState == STATE_WRITEBACK & (CMOp[3] & CacheBusAck))); assign SelWriteback = (CurrState == STATE_WRITEBACK & (CMOp[1] | CMOp[2] | ~CacheBusAck)) |