From 1ceea51d8b7574650bb5ef3ea23760ae42fa2130 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 31 May 2023 16:51:00 -0500 Subject: [PATCH] Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. --- config/shared/parameter-defs.vh | 2 +- sim/verilate | 4 +- src/wally/wallypipelinedsoc.sv | 19 +++---- testbench/common/instrNameDecTB.sv | 3 + testbench/testbench.sv | 90 ++++++++++++++++++++++++------ 5 files changed, 87 insertions(+), 31 deletions(-) diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 271fc7fe8..78efd582d 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -76,7 +76,7 @@ parameter cvw_t P = '{ // *** definitely need to fix this. // it thinks we are casting from the enum type to BPRED_TYPE. BPRED_TYPE : BPRED_TYPE, - /* verilator lint_off ENUMVALUE */ + /* verilator lint_on ENUMVALUE */ BPRED_SIZE : BPRED_SIZE, BPRED_NUM_LHR : BPRED_NUM_LHR, BTB_SIZE : BTB_SIZE, diff --git a/sim/verilate b/sim/verilate index 345e17ab9..9555322f9 100755 --- a/sim/verilate +++ b/sim/verilate @@ -7,8 +7,8 @@ verilator=`which verilator` basepath=$(dirname $0)/.. #for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do for config in rv64gc; do - echo "$config linting..." - if !($verilator --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/testbench/testbench.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + echo "$config simulating..." + if !($verilator --timescale "1ns/1ns" --timing --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/testbench/common/*.sv $basepath/testbench/testbench.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 03974fe51..14e085260 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -26,22 +26,19 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "config.vh" -//import cvw::*; // global CORE-V-Wally parameters - -module wallypipelinedsoc import cvw::*; ( +module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( input logic clk, input logic reset_ext, // external asynchronous reset pin output logic reset, // reset synchronized to clk to prevent races on release // AHB Interface - input logic [AHBW-1:0] HRDATAEXT, + input logic [P.AHBW-1:0] HRDATAEXT, input logic HREADYEXT, HRESPEXT, output logic HSELEXT, // outputs to external memory, shared with uncore memory output logic HCLK, HRESETn, - output logic [PA_BITS-1:0] HADDR, - output logic [AHBW-1:0] HWDATA, - output logic [XLEN/8-1:0] HWSTRB, + output logic [P.PA_BITS-1:0] HADDR, + output logic [P.AHBW-1:0] HWDATA, + output logic [P.XLEN/8-1:0] HWSTRB, output logic HWRITE, output logic [2:0] HSIZE, output logic [2:0] HBURST, @@ -64,14 +61,12 @@ module wallypipelinedsoc import cvw::*; ( ); // Uncore signals - logic [AHBW-1:0] HRDATA; // from AHB mux in uncore + logic [P.AHBW-1:0] HRDATA; // from AHB mux in uncore logic HRESP; // response from AHB logic MTimerInt, MSwInt;// timer and software interrupts from CLINT logic [63:0] MTIME_CLINT; // from CLINT to CSRs logic MExtInt,SExtInt; // from PLIC - `include "parameter-defs.vh" - // synchronize reset to SOC clock domain synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); @@ -83,7 +78,7 @@ module wallypipelinedsoc import cvw::*; ( ); // instantiate uncore if a bus interface exists - if (BUS_SUPPORTED) begin : uncore + if (P.BUS_SUPPORTED) begin : uncore uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, diff --git a/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv index dd993e715..58f1ea9fc 100644 --- a/testbench/common/instrNameDecTB.sv +++ b/testbench/common/instrNameDecTB.sv @@ -250,7 +250,10 @@ module instrNameDecTB( else if (funct7[6:2] == 5'b00100) name = "FSGNJX"; else if (funct7[6:2] == 5'b10100) name = "FEQ"; else name = "ILLEGAL"; + /* verilator lint_off CASEOVERLAP */ + // *** RT: definitely take a look at this. This overlaps with 10'b1010011_000 10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD"; + /* verilator lint_on CASEOVERLAP */ else if (funct7[6:2] == 5'b00001) name = "FSUB"; else if (funct7[6:2] == 5'b00010) name = "FMUL"; else if (funct7[6:2] == 5'b00011) name = "FDIV"; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 6184cefb0..c2e2212e8 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -26,6 +26,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" +`include "config.vh" `include "tests.vh" `define PrintHPMCounters 0 @@ -33,7 +34,12 @@ `define I_CACHE_ADDR_LOGGER 0 `define D_CACHE_ADDR_LOGGER 0 +import cvw::*; + + module testbench; + /* verilator lint_off WIDTHTRUNC */ + /* verilator lint_off WIDTHEXPAND */ parameter DEBUG=0; parameter TEST="none"; @@ -42,7 +48,8 @@ module testbench; parameter SIGNATURESIZE = 5000000; - int test, i, errors, totalerrors; + int test, errors, totalerrors; + logic [`PA_BITS-1:0] i; logic [31:0] sig32[0:SIGNATURESIZE]; logic [`XLEN-1:0] signature[0:SIGNATURESIZE]; logic [`XLEN-1:0] testadr, testadrNoBase; @@ -66,6 +73,8 @@ module testbench; logic HCLK, HRESETn; logic [`XLEN-1:0] PCW; + `include "parameter-defs.vh" + string ProgramAddrMapFile, ProgramLabelMapFile; integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; @@ -190,7 +199,7 @@ module testbench; assign HRDATAEXT = 0; end - if(`FPGA) begin : sdcard + if(P.FPGA) begin : sdcard sdModel sdcard (.sdClk(SDCCLK), .cmd(SDCCmd), @@ -204,7 +213,7 @@ module testbench; assign SDCDat = '0; end - wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); @@ -239,9 +248,8 @@ module testbench; // not initialized the compare results in an 'x' which propagates through // the design. if (TEST == "coremark") - for (i=MemStartAddr; i>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)]; if(`DCACHE_SUPPORTED) begin - localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; - localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; - localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; - localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; - localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; - localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; + //localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; + localparam numlines = DCACHE_WAYSIZEINBYTES*8/DCACHE_LINELENINBITS; + //localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; + localparam numways = DCACHE_NUMWAYS; + //localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; + localparam linebytelen = DCACHE_LINELENINBITS/8; + localparam linelen = DCACHE_LINELENINBITS; + //localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; + localparam sramlen = 128; + //localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; + localparam cachesramwords = DCACHE_LINELENINBITS/sramlen; localparam numwords = sramlen/`XLEN; localparam lognumlines = $clog2(numlines); localparam loglinebytelen = $clog2(linebytelen); @@ -772,6 +820,8 @@ module DCacheFlushFSM end end flop #(1) doneReg(.clk, .d(start), .q(done)); + /* verilator lint_on WIDTHTRUNC */ + /* verilator lint_on WIDTHEXPAND */ endmodule module copyShadow @@ -790,6 +840,8 @@ module copyShadow output logic CacheDirty); + /* verilator lint_off WIDTHTRUNC */ + /* verilator lint_off WIDTHEXPAND */ always_ff @(posedge clk) begin if(start) begin CacheTag = tag; @@ -800,9 +852,13 @@ module copyShadow end end + /* verilator lint_on WIDTHTRUNC */ + /* verilator lint_on WIDTHEXPAND */ endmodule task automatic updateProgramAddrLabelArray; + /* verilator lint_off WIDTHTRUNC */ + /* verilator lint_off WIDTHEXPAND */ input string ProgramAddrMapFile, ProgramLabelMapFile; inout integer ProgramAddrLabelArray [string]; // Gets the memory location of begin_signature @@ -821,5 +877,7 @@ task automatic updateProgramAddrLabelArray; end $fclose(ProgramLabelMapFP); $fclose(ProgramAddrMapFP); + /* verilator lint_on WIDTHTRUNC */ + /* verilator lint_on WIDTHEXPAND */ endtask