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I think I solved the AMO/store hazard issue introduced by removing the store delay hazard.

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This commit is contained in:
Rose Thompson 2023-12-14 16:31:02 -06:00
parent bb712d6860
commit 1ca9a8be6d
2 changed files with 8 additions and 3 deletions
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6
src/cache/cachefsm.sv vendored
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@ -105,6 +105,8 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
assign CacheAccess = (|CacheRW) & ((CurrState == STATE_READY & ~Stall & ~FlushStage) | (CurrState == STATE_READ_HOLD & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
assign CacheMiss = CacheAccess & ~CacheHit;
assign StoreHazard = CacheRWNext[1] & CacheRW[0] & ~CacheRW[1];
// special case on reset. When the fsm first exists reset the
// PCNextF will no longer be pointing to the correct address.
// But PCF will be the reset vector.
@ -121,7 +123,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH;
else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; // exclusion-tag: icache FETCHStatement
else if(AnyMiss | CMOWriteback) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement
else if(CacheRWNext[1] & CacheRW[0]) NextState = STATE_READ_HOLD;
else if(StoreHazard) NextState = STATE_READ_HOLD;
else NextState = STATE_READY;
STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE;
else if(CacheBusAck) NextState = STATE_READY;
@ -147,7 +149,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
// com back to CPU
assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & (CurrState == STATE_READ_HOLD));
assign StallConditions = FlushCache | AnyMiss | CMOWriteback | (CacheRWNext[1] & CacheRW[0]);
assign StallConditions = FlushCache | AnyMiss | CMOWriteback | (StoreHazard);
assign CacheStall = (CurrState == STATE_READY & StallConditions) | // exclusion-tag: icache StallStates
(CurrState == STATE_FETCH) |
(CurrState == STATE_WRITEBACK) |

5
src/ieu/controller.sv
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@ -429,5 +429,8 @@ module controller import cvw::*; #(parameter cvw_t P) (
// atomic operations are also detected as MemRWD[1]
// *** RT: Remove this after updating the cache.
// *** RT: Check that atomic after atomic works correctly.
assign StoreStallD = ((|CMOpE)) & ((|CMOpD));
//assign StoreStallD = ((|CMOpE)) & ((|CMOpD));
logic AMOHazard;
assign AMOHazard = &MemRWM & MemRWE[1];
assign StoreStallD = ((|CMOpE) & (|CMOpD)) | AMOHazard;
endmodule