From 1ca9a8be6dc97e7c6c70579cd3d4565a72be4c5e Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 14 Dec 2023 16:31:02 -0600 Subject: [PATCH] I think I solved the AMO/store hazard issue introduced by removing the store delay hazard. --- src/cache/cachefsm.sv | 6 ++++-- src/ieu/controller.sv | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 94579827f..cfc0a8c16 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -105,6 +105,8 @@ module cachefsm import cvw::*; #(parameter cvw_t P, assign CacheAccess = (|CacheRW) & ((CurrState == STATE_READY & ~Stall & ~FlushStage) | (CurrState == STATE_READ_HOLD & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW assign CacheMiss = CacheAccess & ~CacheHit; + assign StoreHazard = CacheRWNext[1] & CacheRW[0] & ~CacheRW[1]; + // special case on reset. When the fsm first exists reset the // PCNextF will no longer be pointing to the correct address. // But PCF will be the reset vector. @@ -121,7 +123,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; // exclusion-tag: icache FETCHStatement else if(AnyMiss | CMOWriteback) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement - else if(CacheRWNext[1] & CacheRW[0]) NextState = STATE_READ_HOLD; + else if(StoreHazard) NextState = STATE_READ_HOLD; else NextState = STATE_READY; STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; else if(CacheBusAck) NextState = STATE_READY; @@ -147,7 +149,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, // com back to CPU assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & (CurrState == STATE_READ_HOLD)); - assign StallConditions = FlushCache | AnyMiss | CMOWriteback | (CacheRWNext[1] & CacheRW[0]); + assign StallConditions = FlushCache | AnyMiss | CMOWriteback | (StoreHazard); assign CacheStall = (CurrState == STATE_READY & StallConditions) | // exclusion-tag: icache StallStates (CurrState == STATE_FETCH) | (CurrState == STATE_WRITEBACK) | diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 11f87125a..d7c89ca47 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -429,5 +429,8 @@ module controller import cvw::*; #(parameter cvw_t P) ( // atomic operations are also detected as MemRWD[1] // *** RT: Remove this after updating the cache. // *** RT: Check that atomic after atomic works correctly. - assign StoreStallD = ((|CMOpE)) & ((|CMOpD)); + //assign StoreStallD = ((|CMOpE)) & ((|CMOpD)); + logic AMOHazard; + assign AMOHazard = &MemRWM & MemRWE[1]; + assign StoreStallD = ((|CMOpE) & (|CMOpD)) | AMOHazard; endmodule