From 1c1acc467e84ce6268152326eecb6830f3a591ae Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 26 Oct 2024 02:01:09 -0700 Subject: [PATCH] Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0 --- src/uncore/spi_apb.sv | 4 +- .../references/WALLY-spi-01.reference_output | 40 +++++++++---------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index 57260e769..54a072ac9 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -234,9 +234,9 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( // SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1)) // Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv // Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase - // When SckDiv is 0, count doesn't work and SCLKenable is simply PCLK + // When SckDiv is 0, count doesn't work and SCLKenable is simply PCLK *** dh 10/26/24: this logic is seriously broken. SCLK is not scaled to PCLK/(2*(SckDiv + 1)). SCLKenableEarly doesn't work right for SckDiv=0 assign ZeroDiv = ~|(SckDiv[10:0]); - assign SCLKenable = ZeroDiv ? PCLK : (DivCounter == SckDiv); + assign SCLKenable = ZeroDiv ? 1 : (DivCounter == SckDiv); assign SCLKenableEarly = ((DivCounter + 12'b1) == SckDiv); always_ff @(posedge PCLK) if (~PRESETn) DivCounter <= '0; diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output index f62d9b088..425866ac2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output @@ -32,59 +32,59 @@ 00000003 -00000074 +00000074 # spi_burst_send -00000063 +00000063 # spi_burst_send -00000052 +00000052 # spi_burst_send -00000041 +00000041 # spi_burst_send -000000A1 +000000A1 # spi_burst_send 00000003 -000000B2 +000000B2 # spi_burst_send 00000001 -000000C3 +000000C3 # spi_burst_send -000000D4 +000000D4 # spi_burst_send 00000003 -000000A4 +000000A4 # tx_data write test 00000001 -000000B4 +000000B4 # tx_data write test -000000A5 +000000A5 # spi_burst_send -000000B5 +000000B5 # spi_burst_send -000000C5 +000000C5 # spi_burst_send -000000D5 +000000D5 # spi_burst_send -000000A7 +000000A7 # spi_burst_send -000000B7 +000000B7 # spi_burst_send -000000C7 +000000C7 # spi_burst_send 00000002 -000000D7 +000000D7 # spi_burst_send 00000000 00000011 #basic read write -000000FF +000000FF # first test sck_div -000000AE +000000AE # min sck_div first spi_burst_send 000000AD