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Fixed formatting
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@ -27,20 +27,20 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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module negateintres import cvw::*; #(parameter cvw_t P) (
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module negateintres import cvw::*; #(parameter cvw_t P) (
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input logic Signed, // is the integer input signed
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input logic Signed, // is the integer input signed
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input logic Int64, // is the integer input 64-bits
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input logic Int64, // is the integer input 64-bits
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input logic Plus1, // should one be added for rounding?
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input logic Plus1, // should one be added for rounding?
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input logic Xs, // X sign
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input logic Xs, // X sign
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input logic [P.NORMSHIFTSZ-1:0] Shifted, // output from normalization shifter
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input logic [P.NORMSHIFTSZ-1:0] Shifted, // output from normalization shifter
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output logic [1:0] CvtNegResMsbs, // most signigficant bits of possibly negated result
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output logic [1:0] CvtNegResMsbs, // most signigficant bits of possibly negated result
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output logic [P.XLEN+1:0] CvtNegRes // possibly negated integer result
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output logic [P.XLEN+1:0] CvtNegRes // possibly negated integer result
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);
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);
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logic [P.XLEN+1:0] CvtPreRes; // integer result with rounding
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logic [P.XLEN+1:0] CvtPreRes; // integer result with rounding
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logic [2:0] CvtNegResMsbs3; // first three msbs of possibly negated result
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logic [2:0] CvtNegResMsbs3; // first three msbs of possibly negated result
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// round and negate the positive res if needed
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// round and negate the positive res if needed
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assign CvtPreRes = {2'b0, Shifted[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.XLEN]}+{{P.XLEN+1{1'b0}}, Plus1};
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assign CvtPreRes = {2'b0, Shifted[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.XLEN]}+{{P.XLEN+1{1'b0}}, Plus1};
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mux2 #(P.XLEN+2) resmux(CvtPreRes, -CvtPreRes, Xs, CvtNegRes);
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mux2 #(P.XLEN+2) resmux(CvtPreRes, -CvtPreRes, Xs, CvtNegRes);
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// select 2 most significant bits
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// select 2 most significant bits
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