From 1badc8a8c5f52bc4de485ae5cd3a42127861dc22 Mon Sep 17 00:00:00 2001 From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com> Date: Sun, 30 Jul 2023 18:00:39 -0700 Subject: [PATCH] Fixed formatting --- src/fpu/postproc/negateintres.sv | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv index 069a1a2b9..d0aaf760b 100644 --- a/src/fpu/postproc/negateintres.sv +++ b/src/fpu/postproc/negateintres.sv @@ -27,20 +27,20 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module negateintres import cvw::*; #(parameter cvw_t P) ( - input logic Signed, // is the integer input signed - input logic Int64, // is the integer input 64-bits - input logic Plus1, // should one be added for rounding? - input logic Xs, // X sign + input logic Signed, // is the integer input signed + input logic Int64, // is the integer input 64-bits + input logic Plus1, // should one be added for rounding? + input logic Xs, // X sign input logic [P.NORMSHIFTSZ-1:0] Shifted, // output from normalization shifter - output logic [1:0] CvtNegResMsbs, // most signigficant bits of possibly negated result + output logic [1:0] CvtNegResMsbs, // most signigficant bits of possibly negated result output logic [P.XLEN+1:0] CvtNegRes // possibly negated integer result ); logic [P.XLEN+1:0] CvtPreRes; // integer result with rounding - logic [2:0] CvtNegResMsbs3; // first three msbs of possibly negated result + logic [2:0] CvtNegResMsbs3; // first three msbs of possibly negated result // round and negate the positive res if needed - assign CvtPreRes = {2'b0, Shifted[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.XLEN]}+{{P.XLEN+1{1'b0}}, Plus1}; + assign CvtPreRes = {2'b0, Shifted[P.NORMSHIFTSZ-1:P.NORMSHIFTSZ-P.XLEN]}+{{P.XLEN+1{1'b0}}, Plus1}; mux2 #(P.XLEN+2) resmux(CvtPreRes, -CvtPreRes, Xs, CvtNegRes); // select 2 most significant bits