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UpdateDA cleanup: don't assert UpdateDA when there is no SVADU

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This commit is contained in:
David Harris 2023-10-04 09:57:13 -07:00
parent d526d28804
commit 19a6bbb01b
2 changed files with 2 additions and 2 deletions
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1
src/ifu/spill.sv
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@ -83,6 +83,7 @@ module spill import cvw::*; #(parameter cvw_t P) (
assign SpillF = CacheableF ? SpillCachedF : SpillUncachedF; assign SpillF = CacheableF ? SpillCachedF : SpillUncachedF;
end else end else
assign SpillF = PCF[1]; // *** might relax - only spill if next instruction is uncompressed assign SpillF = PCF[1]; // *** might relax - only spill if next instruction is uncompressed
// Don't take the spill if there is a stall, TLB miss, or hardware update to the D/A bits
assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF)); assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF));
always_ff @(posedge clk) always_ff @(posedge clk)

3
src/mmu/tlb/tlbcontrol.sv
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@ -115,8 +115,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
end end
// Determine wheter to update DA bits. With SVADU, it is done in hardware // Determine wheter to update DA bits. With SVADU, it is done in hardware
if (P.SVADU_SUPPORTED) assign UpdateDA = PreUpdateDA & Translate & TLBHit & ~TLBPageFault & ENVCFG_HADE; assign UpdateDA = P.SVADU_SUPPORTED & PreUpdateDA & Translate & TLBHit & ~TLBPageFault & ENVCFG_HADE;
else assign UpdateDA = PreUpdateDA;
// Determine whether page fault occurs // Determine whether page fault occurs
assign PrePageFault = UpperBitsUnequal | Misaligned | ~PTE_V | ImproperPrivilege | (P.XLEN == 64 & (BadPBMT | BadNAPOT | BadReserved)) | (PreUpdateDA & (~P.SVADU_SUPPORTED | ~ENVCFG_HADE)); assign PrePageFault = UpperBitsUnequal | Misaligned | ~PTE_V | ImproperPrivilege | (P.XLEN == 64 & (BadPBMT | BadNAPOT | BadReserved)) | (PreUpdateDA & (~P.SVADU_SUPPORTED | ~ENVCFG_HADE));